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Searched refs:REG_CMD_CTRL (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBT/
H A DINTERN_DVBT.h259 #define REG_CMD_CTRL 0x20CC macro
266 #define REG_CMD_CTRL 0x2F1C macro
272 #define _REG_START REG_CMD_CTRL
273 #define _REG_END REG_CMD_CTRL
275 #define _REG_FSM REG_CMD_CTRL
H A DINTERN_DVBT.c284 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
302 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
304 status &= INTERN_DVBT_WriteReg(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
316 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
385 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
386 status &= INTERN_DVBT_WriteReg(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
411 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBT_Cmd_Packet_Exe_Check()
/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBC/
H A DINTERN_DVBC.c265 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
279 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
281 status &= INTERN_DVBC_WriteReg(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
287 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
334 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
335 status &= INTERN_DVBC_WriteReg(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
356 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, &reg_val); in INTERN_DVBC_Cmd_Packet_Exe_Check()
H A DINTERN_DVBC_Private.h245 #define REG_CMD_CTRL 0x20CC macro
250 #define _REG_START REG_CMD_CTRL
251 #define _REG_END REG_CMD_CTRL
253 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_common.h108 #define REG_CMD_CTRL MBRegBase + 0x1C macro
113 #define _REG_START REG_CMD_CTRL
114 #define _REG_END REG_CMD_CTRL
116 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_common.h119 #define REG_CMD_CTRL MBRegBase + 0x1C macro
124 #define _REG_START REG_CMD_CTRL
125 #define _REG_END REG_CMD_CTRL
127 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_common.h119 #define REG_CMD_CTRL MBRegBase + 0x1C macro
124 #define _REG_START REG_CMD_CTRL
125 #define _REG_END REG_CMD_CTRL
127 #define _REG_FSM REG_CMD_CTRL
H A DhalDMD_INTERN_DVBC.c409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
482 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
483 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_common.h120 #define REG_CMD_CTRL MBRegBase + 0x1C macro
125 #define _REG_START REG_CMD_CTRL
126 #define _REG_END REG_CMD_CTRL
128 #define _REG_FSM REG_CMD_CTRL
H A DhalDMD_INTERN_DVBC.c410 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
483 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
484 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_common.h119 #define REG_CMD_CTRL MBRegBase + 0x1C macro
124 #define _REG_START REG_CMD_CTRL
125 #define _REG_END REG_CMD_CTRL
127 #define _REG_FSM REG_CMD_CTRL
H A DhalDMD_INTERN_DVBC.c409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
482 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
483 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_common.h119 #define REG_CMD_CTRL MBRegBase + 0x1C macro
124 #define _REG_START REG_CMD_CTRL
125 #define _REG_END REG_CMD_CTRL
127 #define _REG_FSM REG_CMD_CTRL
H A DhalDMD_INTERN_DVBC.c409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
482 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
483 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_common.h119 #define REG_CMD_CTRL MBRegBase + 0x1C macro
124 #define _REG_START REG_CMD_CTRL
125 #define _REG_END REG_CMD_CTRL
127 #define _REG_FSM REG_CMD_CTRL
H A DhalDMD_INTERN_DVBC.c409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
482 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
483 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_common.h109 #define REG_CMD_CTRL MBRegBase + 0x1C macro
114 #define _REG_START REG_CMD_CTRL
115 #define _REG_END REG_CMD_CTRL
117 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_common.h127 #define REG_CMD_CTRL MBRegBase + 0x1C macro
132 #define _REG_START REG_CMD_CTRL
133 #define _REG_END REG_CMD_CTRL
135 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_common.h109 #define REG_CMD_CTRL MBRegBase + 0x1C macro
114 #define _REG_START REG_CMD_CTRL
115 #define _REG_END REG_CMD_CTRL
117 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_common.h119 #define REG_CMD_CTRL MBRegBase + 0x1C macro
124 #define _REG_START REG_CMD_CTRL
125 #define _REG_END REG_CMD_CTRL
127 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_common.h120 #define REG_CMD_CTRL MBRegBase + 0x1C macro
125 #define _REG_START REG_CMD_CTRL
126 #define _REG_END REG_CMD_CTRL
128 #define _REG_FSM REG_CMD_CTRL
H A DhalDMD_INTERN_DVBC.c410 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
425 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
483 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL); in INTERN_DVBC_Cmd_Packet_Send()
484 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_common.h117 #define REG_CMD_CTRL MBRegBase + 0x1C macro
122 #define _REG_START REG_CMD_CTRL
123 #define _REG_END REG_CMD_CTRL
125 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_common.h116 #define REG_CMD_CTRL MBRegBase + 0x1C macro
121 #define _REG_START REG_CMD_CTRL
122 #define _REG_END REG_CMD_CTRL
124 #define _REG_FSM REG_CMD_CTRL
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_common.h120 #define REG_CMD_CTRL MBRegBase + 0x1C macro
125 #define _REG_START REG_CMD_CTRL
126 #define _REG_END REG_CMD_CTRL
128 #define _REG_FSM REG_CMD_CTRL

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