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Searched refs:REG_CMD_ADDR (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBT/
H A DINTERN_DVBT.h261 #define REG_CMD_ADDR 0x20CE macro
268 #define REG_CMD_ADDR 0x2F1E macro
H A DINTERN_DVBT.c335 status &= INTERN_DVBT_WriteReg(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
343 status &= INTERN_DVBT_ReadReg(REG_CMD_ADDR, &reg_val); in INTERN_DVBT_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBC/
H A DINTERN_DVBC.c302 status &= INTERN_DVBC_WriteReg(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
306 status &= INTERN_DVBC_ReadReg(REG_CMD_ADDR, &reg_val); in INTERN_DVBC_Cmd_Packet_Send()
H A DINTERN_DVBC_Private.h247 #define REG_CMD_ADDR 0x20CE macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_common.h110 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_common.h121 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_common.h121 #define REG_CMD_ADDR MBRegBase + 0x1E macro
H A DhalDMD_INTERN_DVBC.c449 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_common.h122 #define REG_CMD_ADDR MBRegBase + 0x1E macro
H A DhalDMD_INTERN_DVBC.c450 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_common.h121 #define REG_CMD_ADDR MBRegBase + 0x1E macro
H A DhalDMD_INTERN_DVBC.c449 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_common.h121 #define REG_CMD_ADDR MBRegBase + 0x1E macro
H A DhalDMD_INTERN_DVBC.c449 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_common.h121 #define REG_CMD_ADDR MBRegBase + 0x1E macro
H A DhalDMD_INTERN_DVBC.c449 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_common.h111 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_common.h129 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_common.h111 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_common.h121 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_common.h122 #define REG_CMD_ADDR MBRegBase + 0x1E macro
H A DhalDMD_INTERN_DVBC.c450 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR); in INTERN_DVBC_Cmd_Packet_Send()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_common.h119 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_common.h118 #define REG_CMD_ADDR MBRegBase + 0x1E macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_common.h122 #define REG_CMD_ADDR MBRegBase + 0x1E macro

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