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Searched refs:REG_CLK_EVD_PPU_SW_DIV_10 (Results 1 – 6 of 6) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h423 #define REG_CLK_EVD_PPU_SW_DIV_10 BITS(13:9, 10) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h423 #define REG_CLK_EVD_PPU_SW_DIV_10 BITS(13:9, 10) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h435 #define REG_CLK_EVD_PPU_SW_DIV_10 BITS(13:9, 10) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DregHVD_EX.h568 #define REG_CLK_EVD_PPU_SW_DIV_10 BITS(13:9, 10) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DregHVD_EX.h568 #define REG_CLK_EVD_PPU_SW_DIV_10 BITS(13:9, 10) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DregHVD_EX.h568 #define REG_CLK_EVD_PPU_SW_DIV_10 BITS(13:9, 10) macro