Searched refs:REG_CLKGEN1_DC0_STC5_CW_L (Results 1 – 2 of 2) sorted by relevance
185 #define REG_CLKGEN1_DC0_STC5_CW_L 0x5D macro
2305 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_L) = 0x0000; in HAL_TSP_STC_Init()2388 *u32Sync = TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_L); in HAL_TSP_GetSTCSynth()2478 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()