Searched refs:REG_CLKGEN0_TSN_CLK_TS1_SHIFT (Results 1 – 11 of 11) sorted by relevance
214 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8 macro2045 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2046 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2964 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
212 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro2199 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2200 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()3237 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
226 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro2221 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2222 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()3263 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
231 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro2079 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2080 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()3201 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
231 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro2274 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2275 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()3449 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
231 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro2274 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2275 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()3432 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
231 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro2345 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2346 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()3528 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
231 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro2306 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()2307 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS1_SHIFT); in HAL_TSP_SelPad_ClkInv()3489 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
192 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro1662 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
193 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro1652 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
193 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL macro1663 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()