Searched refs:REG_CLKGEN0_TSN_CLK_TS0_SHIFT (Results 1 – 11 of 11) sorted by relevance
213 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0 macro2040 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2041 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2957 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
211 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro2194 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2195 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()3230 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
225 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro2216 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2217 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()3256 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
230 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro2074 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2075 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()3194 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
230 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro2269 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2270 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()3442 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
230 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro2269 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2270 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()3425 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
230 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro2340 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2341 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()3521 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
230 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro2301 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()2302 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS0_SHIFT); in HAL_TSP_SelPad_ClkInv()3482 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
191 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro1655 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
192 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro1645 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
192 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL macro1656 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()