Home
last modified time | relevance | path

Searched refs:REG_CLKGEN0_TSN_CLK (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c210 #define REG_CLKGEN0_TSN_CLK 0x28 macro
2040 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2042 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2045 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2047 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2957 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
2964 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c208 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
2194 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2196 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2199 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2201 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
3230 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3237 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c222 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
2216 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2218 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2221 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2223 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
3256 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3263 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c188 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
1371 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_C… in HAL_TSP_SelPad_ClkInv()
1655 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
1662 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c189 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
1374 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_C… in HAL_TSP_SelPad_ClkInv()
1645 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
1652 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c189 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
1372 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_C… in HAL_TSP_SelPad_ClkInv()
1656 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
1663 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c227 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
2074 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2076 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2079 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2081 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
3194 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3201 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c227 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
2269 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2271 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2274 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2276 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
3442 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3449 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c227 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
2269 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2271 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2274 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2276 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
3425 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3432 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c227 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
2340 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2342 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2345 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2347 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
3521 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3528 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c227 #define REG_CLKGEN0_TSN_CLK 0x28UL macro
2301 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2303 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2306 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2308 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
3482 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3489 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()