| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_sc.c | 287 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_IDCLK2<<10, (BIT(11)|BIT(10))); // clk_idclk2 in Hal_SC_set_ficlk()
291 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_FCLK<<10, (BIT(11)|BIT(10))); // clk_fclk in Hal_SC_set_ficlk()
298 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_IDCLK2<<2, (BIT(3)|BIT(2))); // clk_idclk2 in Hal_SC_set_ficlk()
302 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_FCLK<<2, (BIT(3)|BIT(2))); // clk_fclk in Hal_SC_set_ficlk()
3823 u16OP1_ficlk_status = R2BYTEMSK(REG_CLKGEN0_51_L, 0x0C00); in MHal_SC_OP1_Pattern_backup_setting()
4056 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_FCLK<<10, (BIT(11)|BIT(10))); // clk_idclk2 in MHal_SC_OP1_Pattern_init_setting()
4102 W2BYTEMSK(REG_CLKGEN0_51_L, u16OP1_ficlk_status, (BIT(11)|BIT(10))); // clk_idclk2s in MHal_SC_OP1_Pattern_restore_setting()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_sc.c | 291 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_IDCLK2<<10, (BIT(11)|BIT(10))); // clk_idclk2 in Hal_SC_set_ficlk()
295 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_FCLK<<10, (BIT(11)|BIT(10))); // clk_fclk in Hal_SC_set_ficlk()
302 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_IDCLK2<<2, (BIT(3)|BIT(2))); // clk_idclk2 in Hal_SC_set_ficlk()
306 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_FCLK<<2, (BIT(3)|BIT(2))); // clk_fclk in Hal_SC_set_ficlk()
3857 u16OP1_ficlk_status = R2BYTEMSK(REG_CLKGEN0_51_L, 0x0C00); in MHal_SC_OP1_Pattern_backup_setting()
4090 W2BYTEMSK(REG_CLKGEN0_51_L, CLK_SRC_FCLK<<10, (BIT(11)|BIT(10))); // clk_idclk2 in MHal_SC_OP1_Pattern_init_setting()
4136 W2BYTEMSK(REG_CLKGEN0_51_L, u16OP1_ficlk_status, (BIT(11)|BIT(10))); // clk_idclk2s in MHal_SC_OP1_Pattern_restore_setting()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | mhal_xc_chip_config.h | 642 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | mhal_xc_chip_config.h | 642 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 756 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 754 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 937 #define REG_CLKGEN0_51_L (REG_CHIPTOP_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 943 #define REG_CLKGEN0_51_L (REG_CHIPTOP_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 936 #define REG_CLKGEN0_51_L (REG_CHIPTOP_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 930 #define REG_CLKGEN0_51_L (REG_CHIPTOP_BASE + 0xA2) macro
|
| H A D | mhal_xc_chip_config.h.0 | 929 #define REG_CLKGEN0_51_L (REG_CHIPTOP_BASE + 0xA2)
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 809 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 916 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 877 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 928 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 863 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 933 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 920 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) macro
|