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Searched refs:REG_CLKGEN0_4F_L (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.h186 #define REG_CLKGEN0_4F_L (REG_CHIPTOP_BASE + 0x9E) macro
H A DhalPNL.c1430 W2BYTE(REG_CLKGEN0_4F_L,0x0000); //[3:0]CLK_VBY1_FIFO clock setting in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.h186 #define REG_CLKGEN0_4F_L (REG_CHIPTOP_BASE + 0x9E) macro
H A DhalPNL.c1430 W2BYTE(REG_CLKGEN0_4F_L,0x0000); //[3:0]CLK_VBY1_FIFO clock setting in MHal_PNL_Init_XC_Clk()