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Searched refs:REG_CKG_SC_ROT (Results 1 – 20 of 20) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c2253 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2259 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2264 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c2233 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2239 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2244 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c2320 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2326 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2331 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c2496 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2502 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
2507 MDrv_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c3132 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3138 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3143 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c3083 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3089 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3094 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c3134 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3140 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3145 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c3087 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3093 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3098 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h647 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h653 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h653 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h655 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF ) macro
H A Dmhal_xc_chip_config.h.0654 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF )
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h629 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h729 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h689 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h741 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h679 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h746 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h733 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) macro