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Searched refs:REG_CKG_SC1_ODCLK (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.c716 W2BYTEMSK(REG_CKG_SC1_ODCLK, CKG_SC1_ODCLK_13M, CKG_SC1_ODCLK_MASK); // select 13.5M in MHal_PNL_Init_XC_Clk()
717 … W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h222 #define REG_CKG_SC1_ODCLK REG_CLKGEN0_5E_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.c716 W2BYTEMSK(REG_CKG_SC1_ODCLK, CKG_SC1_ODCLK_13M, CKG_SC1_ODCLK_MASK); // select 13.5M in MHal_PNL_Init_XC_Clk()
717 … W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h222 #define REG_CKG_SC1_ODCLK REG_CLKGEN0_5E_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.c716 W2BYTEMSK(REG_CKG_SC1_ODCLK, CKG_SC1_ODCLK_13M, CKG_SC1_ODCLK_MASK); // select 13.5M in MHal_PNL_Init_XC_Clk()
717 … W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h222 #define REG_CKG_SC1_ODCLK REG_CLKGEN0_5E_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.c716 W2BYTEMSK(REG_CKG_SC1_ODCLK, CKG_SC1_ODCLK_13M, CKG_SC1_ODCLK_MASK); // select 13.5M in MHal_PNL_Init_XC_Clk()
717 … W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
718 W2BYTEMSK(REG_CKG_SC1_ODCLK, DISABLE, CKG_SC1_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h222 #define REG_CKG_SC1_ODCLK REG_CLKGEN0_5E_L macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h833 #define REG_CKG_SC1_ODCLK (REG_CHIPTOP_BASE + 0xBD ) // SC1 output dot clock macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h839 #define REG_CKG_SC1_ODCLK (REG_CHIPTOP_BASE + 0xBD ) // SC1 output dot clock macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h832 #define REG_CKG_SC1_ODCLK (REG_CHIPTOP_BASE + 0xBD ) // SC1 output dot clock macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h826 #define REG_CKG_SC1_ODCLK (REG_CHIPTOP_BASE + 0xBD ) // SC1 output dot clock macro
H A Dmhal_xc_chip_config.h.0825 #define REG_CKG_SC1_ODCLK (REG_CHIPTOP_BASE + 0xBD ) // SC1 output dot clock