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Searched refs:REG_CKG_S2_IDCLK1 (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c244 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
252 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
262 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c291 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
298 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
299 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
308 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
309 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c244 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
252 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
262 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c244 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
252 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
262 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c248 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
255 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
256 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
265 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
266 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c247 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
254 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
255 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
264 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
265 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c248 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
255 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
256 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
265 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
266 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c247 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
254 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
255 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
264 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
265 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c244 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_S2_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
251 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
252 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
261 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, CKG_S2_IDCLK1_XTAL, CKG_S2_IDCLK1_MASK); // Sub window reset… in Hal_SC_ip_software_reset()
262 …MDrv_WriteByteMask(REG_CKG_S2_IDCLK1, u8CLK1Mux, CKG_S2_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h857 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h839 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h903 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h1018 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h973 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h1030 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h967 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h1035 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h1022 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk macro