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Searched refs:REG_CKG_S2_GOP_HDR (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h781 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h763 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h769 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h940 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h934 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
H A Dmhal_xc_chip_config.h.0933 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h827 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h941 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h896 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h953 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h890 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h958 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h945 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) macro
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmvideo.c1285 MDrv_WriteByteMask(REG_CKG_S2_GOP_HDR, CKG_S2_GOP_HDR_EDCLK, CKG_S2_GOP_HDR_MASK); in _MApi_XC_Init_WithoutCreateMutex()
1286 MDrv_WriteRegBit(REG_CKG_S2_GOP_HDR, DISABLE, CKG_S2_GOP_HDR_INVERT); // Not Invert in _MApi_XC_Init_WithoutCreateMutex()
1287 MDrv_WriteRegBit(REG_CKG_S2_GOP_HDR, DISABLE, CKG_S2_GOP_HDR_GATED); in _MApi_XC_Init_WithoutCreateMutex()
H A Dmvideo.c.01282 MDrv_WriteByteMask(REG_CKG_S2_GOP_HDR, CKG_S2_GOP_HDR_EDCLK, CKG_S2_GOP_HDR_MASK);
1283 MDrv_WriteRegBit(REG_CKG_S2_GOP_HDR, DISABLE, CKG_S2_GOP_HDR_INVERT); // Not Invert
1284 MDrv_WriteRegBit(REG_CKG_S2_GOP_HDR, DISABLE, CKG_S2_GOP_HDR_GATED);