| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 810 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 792 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 856 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 971 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 926 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 983 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 920 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 988 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 975 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk macro
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| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mvideo.c | 557 …MDrv_WriteRegBit(REG_CKG_S2_FCLK, ENABLE, CKG_S2_FCLK_GATED); // Enable… in MApi_XC_Exit_U2()
1242 …MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_DEFAULT, CKG_S2_FCLK_MASK); // s… in _MApi_XC_Init_WithoutCreateMutex()
1243 …MDrv_WriteRegBit(REG_CKG_S2_FCLK, DISABLE, CKG_S2_FCLK_INVERT); // Not I… in _MApi_XC_Init_WithoutCreateMutex()
1244 …MDrv_WriteRegBit(REG_CKG_S2_FCLK, DISABLE, CKG_S2_FCLK_GATED); // Enabl… in _MApi_XC_Init_WithoutCreateMutex()
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| H A D | mvideo.c.0 | 554 …MDrv_WriteRegBit(REG_CKG_S2_FCLK, ENABLE, CKG_S2_FCLK_GATED); // Enable…
1239 …MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_DEFAULT, CKG_S2_FCLK_MASK); // s…
1240 …MDrv_WriteRegBit(REG_CKG_S2_FCLK, DISABLE, CKG_S2_FCLK_INVERT); // Not I…
1241 …MDrv_WriteRegBit(REG_CKG_S2_FCLK, DISABLE, CKG_S2_FCLK_GATED); // Enabl…
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| H A D | mdrv_sc_scaling.c | 3729 …bPstScalingDownCheck = ((MDrv_ReadByte(REG_CKG_S2_FCLK) & CKG_S2_FCLK_MASK) == CKG_S2_FCLK_172MHZ)… in MDrv_SC_set_postscaling_ratio()
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| H A D | mdrv_sc_scaling.c.0 | 3713 …bPstScalingDownCheck = ((MDrv_ReadByte(REG_CKG_S2_FCLK) & CKG_S2_FCLK_MASK) == CKG_S2_FCLK_172MHZ)…
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_sc.c | 3424 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
3431 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_sc.c | 3629 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
3636 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_sc.c | 3909 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
3916 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_sc.c | 4259 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
4266 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_sc.c | 4279 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
4286 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_sc.c | 4567 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
4574 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_sc.c | 4567 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
4574 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
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