Home
last modified time | relevance | path

Searched refs:REG_CKG_PDW1 (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c1228 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1229 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_Init()
1300 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1470 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1570 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
1934 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
3315 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c1229 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1230 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_Init()
1301 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1471 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1571 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
1935 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
3317 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c686 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
687 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
1285 MDrv_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c838 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
839 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
1431 MDrv_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_dip.c797 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
798 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
1407 MDrv_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_dip.c799 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
800 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
1409 MDrv_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c719 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
720 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
1320 MDrv_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c1229 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1230 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
1900 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c1229 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1230 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
1900 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h903 #define REG_CKG_PDW1 (REG_CHIPTOP_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h909 #define REG_CKG_PDW1 (REG_CHIPTOP_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h902 #define REG_CKG_PDW1 (REG_CHIPTOP_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h896 #define REG_CKG_PDW1 (REG_CHIPTOP_BASE + 0xBF ) macro
H A Dmhal_xc_chip_config.h.0895 #define REG_CKG_PDW1 (REG_CHIPTOP_BASE + 0xBF )
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h772 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h879 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h840 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h891 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h826 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h896 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h883 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_dip.c1568 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1855 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
4268 …MDrv_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable clock in HAL_XC_DIP_InterruptDetach()