| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mdrv_sc_pip.c | 727 … MDrv_WriteRegBit(REG_CKG_IDCLK1, DISABLE, CKG_IDCLK1_INVERT); // Not Invert in MDrv_XC_EnableCLK_for_SUB()
728 … MDrv_WriteRegBit(REG_CKG_IDCLK1, DISABLE, CKG_IDCLK1_GATED); // Enable clock in MDrv_XC_EnableCLK_for_SUB()
743 MDrv_WriteRegBit(REG_CKG_IDCLK1, ENABLE, CKG_IDCLK1_INVERT); // Not Invert in MDrv_XC_EnableCLK_for_SUB()
744 … MDrv_WriteRegBit(REG_CKG_IDCLK1, ENABLE, CKG_IDCLK1_GATED); // Enable clock in MDrv_XC_EnableCLK_for_SUB()
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| H A D | mdrv_sc_pip.c.0 | 727 … MDrv_WriteRegBit(REG_CKG_IDCLK1, DISABLE, CKG_IDCLK1_INVERT); // Not Invert
728 … MDrv_WriteRegBit(REG_CKG_IDCLK1, DISABLE, CKG_IDCLK1_GATED); // Enable clock
743 MDrv_WriteRegBit(REG_CKG_IDCLK1, ENABLE, CKG_IDCLK1_INVERT); // Not Invert
744 … MDrv_WriteRegBit(REG_CKG_IDCLK1, ENABLE, CKG_IDCLK1_GATED); // Enable clock
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_ip.c | 196 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
203 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
204 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
213 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| H A D | mhal_dip.c | 1050 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1108 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_ip.c | 196 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
203 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
204 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
213 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| H A D | mhal_dip.c | 1033 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1095 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_ip.c | 216 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| H A D | mhal_offline.c | 399 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // initial to … in Hal_XC_SetOfflineDetectClk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_ip.c | 206 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_ip.c | 226 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
248 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
249 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
258 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
259 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_ip.c | 206 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_ip.c | 206 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_ip.c | 207 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_ip.c | 216 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_ip.c | 216 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| H A D | mhal_offline.c | 394 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // initial to … in Hal_XC_SetOfflineDetectClk()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_ip.c | 207 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_ip.c | 216 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_ip.c | 207 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_ip.c | 207 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_ip.c | 206 MS_U8 u8CLK1Mux = MDrv_ReadByte(REG_CKG_IDCLK1); //Sub window in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/ |
| H A D | regCLKGEN.h | 432 #define REG_CKG_IDCLK1 0x1E3E macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/ |
| H A D | regCLKGEN.h | 432 #define REG_CKG_IDCLK1 0x1E3E macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/ |
| H A D | regCLKGEN.h | 432 #define REG_CKG_IDCLK1 0x1E3EUL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/ |
| H A D | regCLKGEN.h | 432 #define REG_CKG_IDCLK1 0x1E3EUL macro
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