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Searched refs:REG_ADC_ATOP_51_L (Results 1 – 25 of 37) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_adc.c2117 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2140 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2185 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_adc.c2117 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2140 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2185 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_adc.c2079 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2102 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2147 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_adc.c2079 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2102 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2147 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_adc.c2095 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2118 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2163 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_adc.c2079 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2102 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2147 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_adc.c2209 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2232 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2277 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_adc.c2201 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2224 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2269 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_adc.c2201 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2224 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2269 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_adc.c2201 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2224 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2269 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_adc.c2201 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0xE0 , 0xF0 ); // Change mux to null mux. in Hal_ADC_set_cvbs_out()
2224 MDrv_WriteByteMask(REG_ADC_ATOP_51_L, 0x00 , 0xF0 ); in Hal_ADC_set_cvbs_out()
2269 MDrv_WriteByte(REG_ADC_ATOP_51_L,0x0F); in Hal_ADC_set_cvbs_out()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
H A Dmhal_adctbl.c2592 { DRV_ADC_REG(REG_ADC_ATOP_51_L), 0x0F, 0x00, 0x00/*CVBS0*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
H A Dmhal_adctbl.c2592 { DRV_ADC_REG(REG_ADC_ATOP_51_L), 0x0F, 0x00, 0x00/*CVBS0*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
H A Dmhal_adctbl.c2543 { DRV_ADC_REG(REG_ADC_ATOP_51_L), 0x0F, 0x00, 0x00/*CVBS0*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_adc_atop.h267 #define REG_ADC_ATOP_51_L (REG_ADC_ATOP_BASE + 0xA2) macro
H A Dmhal_adctbl.c2592 { DRV_ADC_REG(REG_ADC_ATOP_51_L), 0x0F, 0x00, 0x00/*CVBS0*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c2700 { DRV_ADC_REG(REG_ADC_ATOP_51_L), 0x0F, 0x00, 0x00/*CVBS0*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c2700 { DRV_ADC_REG(REG_ADC_ATOP_51_L), 0x0F, 0x00, 0x00/*CVBS0*/,

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