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Searched refs:REG_ADC_ATOP_15_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_adc.c625 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
632 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
642 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
643 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
644 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
652 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
653 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
654 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_adc.c625 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
632 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
642 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
643 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
644 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
652 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
653 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
654 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_adc.c628 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
635 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
645 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
646 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
647 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
655 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
656 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
657 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_adc.c625 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
632 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
642 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
643 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
644 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
652 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
653 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
654 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_adc.c630 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
637 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
647 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
648 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
649 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
657 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
658 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
659 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_adc.c630 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
637 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
647 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
648 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
649 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
657 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
658 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
659 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_adc.c630 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
637 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
647 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
648 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
649 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
657 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
658 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
659 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_adc.c630 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
637 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
647 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
648 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
649 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
657 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
658 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
659 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_adc.c630 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
637 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
647 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
648 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
649 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
657 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
658 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
659 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_adc.c702 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
709 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
719 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
720 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
728 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
729 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_adc.c702 return ( (MS_U8) R2BYTEMSK(REG_ADC_ATOP_15_L, BMASK(9:0))); in Hal_ADC_get_phase()
709 return R2BYTEMSK(REG_ADC_ATOP_15_L,BMASK((6+u16ADCPllMod):0)); in Hal_ADC_get_phaseEx()
719 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value+1, BMASK(9:0)); in Hal_ADC_set_phase()
720 W2BYTEMSK(REG_ADC_ATOP_15_L, u8Value, BMASK(9:0)); in Hal_ADC_set_phase()
728 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value+1, u16Mask); in Hal_ADC_set_phaseEx()
729 W2BYTEMSK(REG_ADC_ATOP_15_L, u16Value, u16Mask); in Hal_ADC_set_phaseEx()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_adc_atop.h147 #define REG_ADC_ATOP_15_L (REG_ADC_ATOP_BASE + 0x2A) macro

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