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Searched refs:R2_REG_STOP (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/cpu/hal/maldives/cpu/
H A DhalCPU.c437 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
509 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
510 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h130 #define R2_REG_STOP (R2_REG_BASE + 0x0080) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/mustang/cpu/
H A DhalCPU.c437 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
509 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
510 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h130 #define R2_REG_STOP (R2_REG_BASE + 0x0080) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/k6lite/cpu/
H A DhalCPU.c437 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
517 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
518 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/kano/cpu/
H A DhalCPU.c437 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
517 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
518 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/k7u/cpu/
H A DhalCPU.c437 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
517 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
518 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/k6/cpu/
H A DhalCPU.c437 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
517 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
518 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/mooney/cpu/
H A DhalCPU.c508 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
577 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); //miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
578 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); //sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h131 #define R2_REG_STOP (R2_REG_BASE + 0x0080UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/messi/cpu/
H A DhalCPU.c508 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
575 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); //miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
576 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); //sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h131 #define R2_REG_STOP (R2_REG_BASE + 0x0080UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/mainz/cpu/
H A DhalCPU.c508 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
575 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); //miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
576 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); //sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h131 #define R2_REG_STOP (R2_REG_BASE + 0x0080UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/curry/cpu/
H A DhalCPU.c438 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
518 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
519 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
H A DregCPU.h129 #define R2_REG_STOP (R2_REG_BASE+0x0080UL) macro
/utopia/UTPA2-700.0.x/modules/cpu/hal/manhattan/cpu/
H A DhalCPU.c561 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
634 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
635 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/maserati/cpu/
H A DhalCPU.c564 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
639 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
640 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/maxim/cpu/
H A DhalCPU.c564 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
637 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
638 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/macan/cpu/
H A DhalCPU.c561 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
634 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
635 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/M7821/cpu/
H A DhalCPU.c564 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
638 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
639 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()
/utopia/UTPA2-700.0.x/modules/cpu/hal/M7621/cpu/
H A DhalCPU.c564 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x00UL); // reg_r2_enable = 0x00 in HAL_COPRO_Disable()
638 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x24UL); // miu_sw_rst and sdram_boot = 1 in HAL_COPRO_Enable()
639 HAL_COPRO_RegWriteByte(R2_REG_STOP, 0x27UL); // sdram_boot and (miu/r2/r2_rst) =1 in HAL_COPRO_Enable()

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