| /utopia/UTPA2-700.0.x/modules/audio/hal/messi/audio/ |
| H A D | ddr_config.h | 38 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0136000 macro
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| H A D | audio_comm2.h | 192 …#define DSP2_CH5_INPUT_DLY_DRAM_BASE (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LIN…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/mainz/audio/ |
| H A D | ddr_config.h | 38 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0136000 macro
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| H A D | audio_comm2.h | 192 …#define DSP2_CH5_INPUT_DLY_DRAM_BASE (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LIN…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/manhattan/audio/ |
| H A D | ddr_config.h | 40 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 macro
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| H A D | audio_comm2.h | 737 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/maldives/audio/ |
| H A D | ddr_config.h | 46 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0000000 macro
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| H A D | audio_comm2.h | 784 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/mooney/audio/ |
| H A D | ddr_config.h | 46 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0000000 macro
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| H A D | audio_comm2.h | 784 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/M7821/audio/ |
| H A D | ddr_config.h | 42 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 macro
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| H A D | audio_comm2.h | 832 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LIN…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/maserati/audio/ |
| H A D | ddr_config.h | 42 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 macro
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| H A D | audio_comm2.h | 866 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LIN…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/M7621/audio/ |
| H A D | ddr_config.h | 42 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 macro
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| H A D | audio_comm2.h | 848 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LIN…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/mustang/audio/ |
| H A D | ddr_config.h | 42 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 macro
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| /utopia/UTPA2-700.0.x/modules/audio/hal/k6/audio/ |
| H A D | ddr_config.h | 92 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x02F0000 macro
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| H A D | audio_comm2.h | 675 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LIN…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/maxim/audio/ |
| H A D | ddr_config.h | 42 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 macro
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| /utopia/UTPA2-700.0.x/modules/audio/hal/kano/audio/ |
| H A D | ddr_config.h | 92 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0000000 macro
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| H A D | audio_comm2.h | 700 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE)…
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| /utopia/UTPA2-700.0.x/modules/audio/hal/macan/audio/ |
| H A D | ddr_config.h | 42 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 macro
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| /utopia/UTPA2-700.0.x/modules/audio/hal/k6lite/audio/ |
| H A D | ddr_config.h | 80 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0000000 macro
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| H A D | audio_comm2.h | 739 ….const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE)…
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