1 #ifndef _DDR_CONFIG_H_ 2 #define _DDR_CONFIG_H_ 3 4 /************************************************ 5 * �ЫO�� Utopia �M DSP �̪��o���ɮפ@�P 6 * 7 * 1. ���Ѥ��n�� ! 8 * 2. �ŧi���n�� .const xxxx = ????; 9 ************************************************/ 10 11 /************************************************ 12 * DSP DDR memory layout 13 *************************************************/ 14 /* DSP DDR size */ 15 #define ADEC__R2_DDR_SIZE 0x5A0000 //5.625 MB 16 #define ASND__R2_DDR_SIZE 0x2E0000 //2.875 MB 17 #define ASND_DSP_DDR_SIZE 0x310000 //3.0625 MB 18 #define COMMON_DDR_SIZE 0x400000 //4.00 MB 19 // Total = 15.5625 MB 20 /* ASND-DSP DDR */ 21 /* SPDIF delay (GP C Bffer) */ 22 #define OFFSET_SPDIF_DLY_DRAM_BASE 0x0000000 23 #define SPDIF_DLY_DRAM_SIZE 0x18000 24 25 #define OFFSET_SE_MAIN_IN_DRAM_ADDR 0x003C000 26 #define SE_MAIN_IN_DRAM_SIZE 0x36000 //216KB, (128ms) multiple of (SE_BUFF2_DMA_24BIT_LINE_SIZE*BYTES_IN_MIU_LINE) 27 28 #define OFFSET_SE_MAIN_OUT_DRAM_ADDR 0x0072000 29 #define SE_MAIN_OUT_DRAM_SIZE 0x6C000 //432KB, (512ms) multiple of (SE_BUFF1_DMA_24BIT_LINE_SIZE*BYTES_IN_MIU_LINE) 30 31 #define OFFSET_DDENC_METADATA_DRAM_ADDR 0x00DF000 32 #define DDENC_METADATA_DRAM_SIZE 0x660 //48 * (PCM1_DRAM_SIZE/2/10/1536) if PCM1_DRAM_SIZE == PCM2_DRAM_SIZE 33 34 #define OFFSET_DM_PREFETCH_DRAM_ADDR 0x00E0000 35 #define DM_PREFETCH_DRAM_SIZE 0x10000 //64KB 36 37 /* HEAD PHONE delay */ 38 #define OFFSET_HEAD_PHONE_DLY_DRAM_BASE 0x00F0000 39 #define HEAD_PHONE_DLY_DRAM_SIZE 0x24000 //144KB 40 41 /* CH5 input delay */ 42 #define OFFSET_CH5_INPUT_DLY_DRAM_BASE 0x0114000 43 #define CH5_INPUT_DLY_DRAM_SIZE 0x24000 //144KB 44 45 /* CH6 input delay */ 46 #define OFFSET_CH6_INPUT_DLY_DRAM_BASE 0x0138000 47 #define CH6_INPUT_DLY_DRAM_SIZE 0x24000 //144KB 48 49 #define OFFSET_ES1_DRAM_ADDR 0x0160000 50 #define ES1_DRAM_SIZE 0x20000 //128KB 51 52 #define OFFSET_ES2_DRAM_ADDR 0x0180000 53 #define ES2_DRAM_SIZE 0x20000 //128KB 54 55 #define OFFSET_ES3_DRAM_ADDR 0x01A0000 56 #define ES3_DRAM_SIZE 0x20000 //128KB 57 58 #define OFFSET_ES4_DRAM_ADDR 0x01C0000 59 #define ES4_DRAM_SIZE 0x20000 //128KB 60 61 #define OFFSET_SIF1_DRAM_ADDR 0x01E0000 62 #define SIF1_DRAM_SIZE 0x8000 // 32KB 63 #define OFFSET_SIF2_DRAM_ADDR 0x01E8000 64 #define SIF2_DRAM_SIZE 0x8000 // 32KB 65 66 #define OFFSET_SER2_DDENC_MCHOUT_DRAM_ADDR 0x1F0000 67 #define SER2_DDENC_MCHOUT_DRAM_SIZE 0xD800 //256 sample * 2byte * 6ch * 18 68 69 #define OFFSET_SER2_OUTPCM_DMX_DRAM_ADDR 0x1FD800 70 #define SER2_OUTPCM_DMX_DRAM_SIZE 0x4800 //256 sample * 2byte * 2ch * 18 71 72 #define OFFSET_DEC1_METADATA1_DRAM_ADDR 0x20C200 73 #define OFFSET_DEC1_METADATA2_DRAM_ADDR 0x20C300 74 #define OFFSET_DEC1_METADATA3_DRAM_ADDR 0x20E940 75 76 #define OFFSET_DEC2_METADATA1_DRAM_ADDR 0x228100 77 #define OFFSET_DEC2_METADATA2_DRAM_ADDR 0x228200 78 #define OFFSET_DEC2_METADATA3_DRAM_ADDR 0x22A840 79 80 #define DEC_METADATA1_DRAM_SIZE 0x100 81 #define DEC_METADATA2_DRAM_SIZE 0x2640 //288 * 34=0x2640, 288 * 34 * 6 = 0xE580 82 #define DEC_METADATA3_DRAM_SIZE 0x19778 83 84 #define OFFSET_KTV_SURROUND_DRAM_ADDR 0x0244000 85 #define KTV_SURROUND_DRAM_SIZE 0x1FE00 //128KB 86 87 #define OFFSET_MSTAR_SURROUND_DRAM_ADDR 0x0264000 88 #define MSTAR_SURROUND_DRAM_SIZE 0x0008000 //32KB (use 12KB) 89 90 #define OFFSET_SIF_OUTPCM_ADDR 0x026C000 91 #define SIF_OUTPCM_DRAM_SIZE 0x2000 //8KB 92 93 /* multi-channel input delay */ 94 #define OFFSET_MULTI_CH_INPUT_DLY_DRAM_BASE 0x026E000 95 #define MULTI_CH_INPUT_DLY_DRAM_SIZE 0x6C000 // 6ch (512 ms), can be adjusted by request //108KB, multiple of (MULTI_CH_INPUT_DELAY_DMA_LINESIZE*BYTES_IN_MIU_LINE) 96 97 /* CH8 input delay */ 98 #define OFFSET_CH8_INPUT_DLY_DRAM_BASE 0x02DA000 99 #define CH8_INPUT_DLY_DRAM_SIZE 0x24000 //144KB 100 101 /* Common DDR */ 102 #define OFFSET_DMA_READER_DRAM_BASE 0x0000000 103 #define DMA_READER_DRAM_SIZE 0x20000 //128KB 104 105 #define OFFSET_SW_DMA_READER_DRAM_BASE 0x0020000 106 #define SW_DMA_READER_DRAM_SIZE 0x10000 //64KB 107 108 #define OFFSET_PCM_CAPTURE1_BUFFER_DRAM_BASE 0x0030000 109 #define OFFSET_PCM_CAPTURE2_BUFFER_DRAM_BASE 0x003C000 110 #define PCM_CAPTURE_BUFFER_DRAM_SIZE 0xC000 //48KB 111 112 #define OFFSET_PCM1_DRAM_ADDR 0x0048000 113 #define PCM1_DRAM_SIZE 0xFF000 //1020KB 114 115 #define OFFSET_HW_DMA_READER2_DRAM_BASE 0x0147000 116 #define HW_DMA_READER2_DRAM_SIZE 0x10000 //64KB 117 118 #define OFFSET_PCM2_DRAM_ADDR 0x015A000 119 #define PCM2_DRAM_SIZE 0xFF000 //1020KB 120 121 #define OFFSET_SPDIF_NONPCM_DRAM_BASE 0x0259000 //216KB 122 #define SPDIF_NONPCM_DRAM_SIZE 0x36000 123 124 #define OFFSET_MP3_ENC_DRAM_BASE 0x028F000 //12KB 125 #define MP3_ENC_DRAM_SIZE 0x3000 126 127 #define OFFSET_OUTPUT_TEMP_DRAM_BASE 0x0292000 //64KB 128 #define OUTPUT_TEMP_DRAM_SIZE 0x10000 129 130 #define OFFSET_HDMI_NONPCM_DRAM_BASE 0x02A0000 131 #define HDMI_NONPCM_DRAM_SIZE 0xD8000 132 133 #define OFFSET_PCM_SWMIXER_CLIENT_INFO_BASE 0x0378000 134 #define PCM_SWMIXER_CLIENT_INFO_SIZE 0x4000 135 136 #define OFFSET_PCM_SWMIXER_CLIENT_BUFFER_BASE 0x037C000 137 #define PCM_SWMIXER_CLIENT_BUFFER_SIZE 0x78000 138 139 #define OFFSET_PCM_SWMIXER_SERVER1_BUFFER_BASE 0x03F4000 140 #define OFFSET_PCM_SWMIXER_SERVER2_BUFFER_BASE 0x03F8000 141 #define PCM_SWMIXER_SERVER_BUFFER_SIZE 0x4000 142 143 #endif //_DDR_CONFIG_H_ 144