1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 #ifndef _AUDIO_COMM2_H_ 79 #define _AUDIO_COMM2_H_ 80 81 82 #include "audio_mbox2.h" 83 #include "ddr_config.h" 84 85 #ifdef _COMPILE_DSP_ 86 #include "Sys_def.h" 87 #endif 88 89 /************************************************ 90 * �ЫO�� Utopia �M DSP �̪��o���ɮפ@�P 91 * 92 * 1. ���Ѥ��n�� ! 93 * 2. �ŧi���n�� .const xxxx = ????; 94 ************************************************/ 95 96 97 /********************************************************* 98 * Version Control 99 *********************************************************/ 100 #define system_version_num 0x000B6D 101 #define dde_version_num 0xD20053 102 #define ms10_dde_version_num 0xD800C9 103 #define btscEnc_version_num 0xEF0127 104 #define fmTx_version_num 0xED010D 105 106 #define AUDIO_DSP2_VERSION (system_version_num + dde_version_num + ms10_dde_version_num + btscEnc_version_num + fmTx_version_num) 107 108 109 /********************************************************* 110 * system define 111 *********************************************************/ 112 #define DSP2_DDP_HDMI_BYPASS_EN 0 113 114 /* Software Feature List */ 115 #define SW_DMA_RDR_EN 0 // SW_DMA_READER1, output by "decoder 5 = 0x8C", disable when HW_DMA_READER2_SUPPORT 116 #define PCM_CAPTURE1_EN 1 // PCM_CAPTURE1 117 #define PCM_CAPTURE2_EN 1 // PCM_CAPTURE2 118 #define PCM_CAPTURE3_EN 0 // PCM_CAPTURE3 119 #define HW_DMA_WRITER1_EN 0 120 121 /* ASND System Channels */ 122 #define SE_PROCESS_FETCH_CHANNELS 14 // SE_Buffer input channels 123 #define SE_PROCESS_STORE_CHANNELS 8 // SE_Buffer output channels 124 #define SPDIF_DELAY_STORE_CHANNELS 2 // SPDIF Buffer channels 125 #define HDMI_DELAY_STORE_CHANNELS 8 // HDMI Buffer channels, 8:_deciFs4x_ 126 #define DELAY_FUNCTION_STORE_CHANNELS 2 // Delay function Buffer channels 127 #define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function Buffer channels 128 129 /* DSP Audio Delay Setting */ 130 #define AUDIO_DELAY_FS 48 // fs = 48kHz 131 #define SPDIF_DELAY_FS 48 132 #define HDMI_DELAY_FS 48 133 #define DMA24BIT_BYTES_IN_WORDS 3 134 #define DMA16BIT_BYTES_IN_WORDS 2 135 136 #define AUDIO_DELAY_LOWER_BOUND 0x20 // min main audio delay , 0x20 = 32 ms 137 #define SPDIF_DELAY_LOWER_BOUND 0x05 // min spdif audio delay, 0x05 = 5 ms 138 #define HDMI_DELAY_LOWER_BOUND 0x05 // min hdmi audio delay , 0x05 = 5 ms 139 #define KTV_DELAY_LOWER_BOUND 0x14 // min ktv audio delay , 0x14 = 20 ms 140 #define AUDIO_DELAY_UPPER_BOUND ((SE_MAIN_IN_DRAM_SIZE/SE_PROCESS_FETCH_CHANNELS + SE_MAIN_OUT_DRAM_SIZE/SE_PROCESS_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 141 #define SPDIF_DELAY_UPPER_BOUND ((SPDIF_DLY_DRAM_SIZE/SPDIF_DELAY_STORE_CHANNELS)/DMA16BIT_BYTES_IN_WORDS/SPDIF_DELAY_FS) //unit : ms 142 #define HDMI_DELAY_UPPER_BOUND ((SE_HDMI_DLY_DRAM_SIZE/2)/DMA16BIT_BYTES_IN_WORDS/HDMI_DELAY_FS) //unit : ms 143 144 #define CH5_INPUT_DLY_UPPER_BOUND ((CH5_INPUT_DLY_DRAM_SIZE/DELAY_FUNCTION_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 145 #define CH6_INPUT_DLY_UPPER_BOUND ((CH6_INPUT_DLY_DRAM_SIZE/DELAY_FUNCTION_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 146 #define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 147 148 /* Audio Ease */ 149 #define AUDIO_EASE_TYPE_LINEAR 0 150 #define AUDIO_EASE_TYPE_INCUBIC 1 151 #define AUDIO_EASE_TYPE_OUTCUBIC 2 152 #define AUDIO_EASE_TYPE_INOUTCUBIC 3 153 154 #define AUDIO_EASE_CH_NONE 0 155 #define AUDIO_EASE_CH_A 1 156 #define AUDIO_EASE_CH_B 2 157 158 /* Sine Tone */ 159 #define SINE_GEN_PARAM_FREQ_48k 137 // (3.1415926*2/8) * 8388608 / 48000 160 #define SINE_GEN_PARAM_FREQ_32k 205 // (3.1415926*2/8) * 8388608 / 32000 161 #define SINE_GEN_PARAM_STEPS 1024 // 1024 steps 162 163 /************************************************ 164 * DSP sram address mapping 165 ************************************************/ 166 /* DSP SRAM Segment */ 167 /* CM */ 168 #define DSP2_CM_MAIN_ADDR 0x0 169 #define DSP2_CM_MAIN_SIZE 0x2000 170 #define DSP2_CM_CODE1_ADDR 0x2000 171 #define DSP2_CM_CODE1_SIZE 0x0100 172 #define DSP2_CM_CODE2_ADDR 0x2100 173 #define DSP2_CM_CODE2_SIZE 0x0000 174 175 /* PM */ 176 #define DSP2_PM_MAIN_ADDR 0x2100 177 #define DSP2_PM_MAIN_SIZE 0x02FF 178 #define DSP2_PM_SEG1_ADDR 0x23FF 179 #define DSP2_PM_SEG1_SIZE 0x2401 180 #define DSP2_PM_SEG2_ADDR 0x4800 181 #define DSP2_PM_SEG2_SIZE 0x0000 182 183 /* Prefetch */ 184 #define DSP2_PM_PREFETCH_DSPADDR 0x10000 // check "arch.sys" 185 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE 186 #define DSP2_PM_PREFETCH2_DSPADDR 0x12000 // check "arch.sys" 187 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE 188 189 /* DM */ 190 #define DSP2_DM_MAIN_ADDR 0x2F00 191 #define DSP2_DM_MAIN_SIZE 0x1100 192 #define DSP2_DM_SEG1A_ADDR 0x0 193 #define DSP2_DM_SEG1A_SIZE 0x2F00 194 #define DSP2_DM_SEG1B_ADDR 0x2F00 195 #define DSP2_DM_SEG1B_SIZE 0x0 196 #define DSP2_DM_SEG2_ADDR 0x2F00 197 #define DSP2_DM_SEG2_SIZE 0x0 198 199 /* XBox */ 200 #define DSP2_XBOX_MAIN_ADDR 0xB800 201 #define DSP2_XBOX_MAIN_SIZE 0x200 202 203 #define ENC_INIT_ADDR DSP2_CM_CODE1_ADDR 204 #define ENC_CM_SEG _cm_code1 205 #define ENC_PM_SEG _pm_ovly1 206 #define ENC_CACHE_SEG _ext_code05 207 #define ENC_FETCH_SEG _ext_fetch1 208 #define ENC_DM_SEG _dm_ovly1a 209 #define ENC_PM_SEG_ADDR DSP2_PM_SEG1_ADDR 210 #define ENC_DM_SEG_ADDR DSP2_DM_SEG1A_ADDR 211 212 /* SND DSP PM vars */ 213 /* common */ 214 #define DSP2PmAddr_mainVer (DSP2_PM_MAIN_ADDR) //0x1900 215 #define DSP2PmAddr_alg1Ver (DSP2_PM_SEG1_ADDR) //0x1BFF // decoder 2 version 216 #define DSP2PmAddr_alg2Ver (DSP2_PM_MAIN_ADDR-1) 217 218 #define DSP2PmAddr_peq48KCoeffAddr (DSP2PmAddr_mainVer + 1) 219 #define DSP2PmAddr_peq32KCoeffAddr (DSP2PmAddr_peq48KCoeffAddr) 220 #define DSP2PmAddr_peqscale48KAddr (DSP2PmAddr_peq48KCoeffAddr + 40 ) 221 #define DSP2PmAddr_peqbandEnAddr (DSP2PmAddr_peqscale48KAddr + 8 ) 222 #define DSP2PmAddr_peqbandDoubleAddr (DSP2PmAddr_peqbandEnAddr + 1 ) 223 #define DSP2PmAddr_hpf48KCoeffAddr (DSP2PmAddr_peqbandDoubleAddr + 1 ) 224 #define DSP2PmAddr_toneSelectAddr (DSP2PmAddr_hpf48KCoeffAddr + 5 ) 225 #define DSP2PmAddr_bass48KCoeffAddr (DSP2PmAddr_toneSelectAddr + 1 ) 226 #define DSP2PmAddr_bassscale48KAddr (DSP2PmAddr_bass48KCoeffAddr + 5 ) 227 #define DSP2PmAddr_treble48KCoeffAddr (DSP2PmAddr_bassscale48KAddr + 1 ) 228 #define DSP2PmAddr_treblescale48KAddr (DSP2PmAddr_treble48KCoeffAddr + 5 ) 229 #define DSP2PmAddr_VolEaseAddr (DSP2PmAddr_treblescale48KAddr + 1 ) 230 231 /* ATV_Enc */ 232 #define DSP2_PM_ATV_Enc_input_attenuation_ADDR (DSP2PmAddr_alg1Ver+1) 233 #define DSP2_PM_ATV_Enc_output_scaling_ADDR (DSP2PmAddr_alg1Ver+2) 234 #define DSP2_PM_BTSC_Enc_output_M_gain_ADDR (DSP2PmAddr_alg1Ver+3) 235 #define DSP2_PM_BTSC_Enc_output_D_gain_ADDR (DSP2PmAddr_alg1Ver+4) 236 #define DSP2_PM_BTSC_Enc_output_SAP_gain_ADDR (DSP2PmAddr_alg1Ver+5) 237 238 /* SND DSP DM vars */ 239 240 /* Extra Box Address */ 241 242 /* sys_param */ 243 #define DSP2XboxAddr_mainVer 0xB800 244 #define DSP2XboxAddr_mainAudioDelay (DSP2XboxAddr_mainVer + 0x01) 245 #define DSP2XboxAddr_spdifDelay (DSP2XboxAddr_mainVer + 0x02) 246 #define DSP2XboxAddr_hpDelay (DSP2XboxAddr_mainVer + 0x03) 247 #define DSP2XboxAddr_hdmiNonPcmSts (DSP2XboxAddr_mainVer + 0x04) 248 #define DSP2XboxAddr_btFrameSize (DSP2XboxAddr_mainVer + 0x05) 249 #define DSP2XboxAddr_ipSecurity (DSP2XboxAddr_mainVer + 0x06) 250 #define DSP2XboxAddr_hdmiDelay (DSP2XboxAddr_mainVer + 0x07) 251 #define DSP2XboxAddr_ch5InputDelay (DSP2XboxAddr_mainVer + 0x08) 252 #define DSP2XboxAddr_ch6InputDelay (DSP2XboxAddr_mainVer + 0x09) 253 #define DSP2XboxAddr_multiChInputDelay (DSP2XboxAddr_mainVer + 0x0A) 254 255 #define DSP2XboxAddr_peq48KCoeffAddr (DSP2XboxAddr_mainVer + 0x10) // len 40 256 #define DSP2XboxAddr_peq32KCoeffAddr (DSP2XboxAddr_peq48KCoeffAddr) 257 #define DSP2XboxAddr_peqscale48KAddr (DSP2XboxAddr_mainVer + 0x38) // len 8 258 #define DSP2XboxAddr_peqbandEnAddr (DSP2XboxAddr_mainVer + 0x40) // len 1 259 #define DSP2XboxAddr_peqbandDoubleAddr (DSP2XboxAddr_mainVer + 0x41) // len 1 260 #define DSP2XboxAddr_hpf48KCoeffAddr (DSP2XboxAddr_mainVer + 0x42) // len 5 261 #define DSP2XboxAddr_toneSelectAddr (DSP2XboxAddr_mainVer + 0x47) // len 1 262 #define DSP2XboxAddr_bass48KCoeffAddr (DSP2XboxAddr_mainVer + 0x48) // len 5 263 #define DSP2XboxAddr_bassscale48KAddr (DSP2XboxAddr_mainVer + 0x4D) // len 1 264 #define DSP2XboxAddr_treble48KCoeffAddr (DSP2XboxAddr_mainVer + 0x4E) // len 5 265 #define DSP2XboxAddr_treblescale48KAddr (DSP2XboxAddr_mainVer + 0x53) // len 1 266 #define DSP2XboxAddr_VolEaseAddr (DSP2XboxAddr_mainVer + 0x54) // len 9 267 268 #define DSP2XboxAddr_peqUpdateFlag (DSP2XboxAddr_mainVer + 0x5D) // len 1 269 #define DSP2XboxAddr_hpUpdateFlag (DSP2XboxAddr_mainVer + 0x5E) // len 1 270 #define DSP2XboxAddr_bassUpdateFlag (DSP2XboxAddr_mainVer + 0x5F) // len 1 271 #define DSP2XboxAddr_trebleUpdateFlag (DSP2XboxAddr_mainVer + 0x60) // len 1 272 #define DSP2XboxAddr_toneUpdateFlag (DSP2XboxAddr_mainVer + 0x61) // len 1 273 #define DSP2XboxAddr_easeAUpdateFlag (DSP2XboxAddr_mainVer + 0x62) // len 1 274 #define DSP2XboxAddr_easeBUpdateFlag (DSP2XboxAddr_mainVer + 0x63) // len 1 275 276 #define DSP2XboxAddr_ATVEnc_input_attenuation_ADDR (DSP2XboxAddr_mainVer + 0x64) // len 1 277 #define DSP2XboxAddr_ATVEnc_output_scaling_ADDR (DSP2XboxAddr_ATVEnc_input_attenuation_ADDR + 1) 278 #define DSP2XboxAddr_BTSCEnc_output_M_gain_ADDR (DSP2XboxAddr_ATVEnc_output_scaling_ADDR + 1) 279 #define DSP2XboxAddr_BTSCEnc_output_D_gain_ADDR (DSP2XboxAddr_BTSCEnc_output_M_gain_ADDR + 1) 280 #define DSP2XboxAddr_BTSCEnc_output_SAP_gain_ADDR (DSP2XboxAddr_BTSCEnc_output_D_gain_ADDR + 1) 281 282 /* sys_info */ 283 #define DSP2XboxAddr_IO_Info1 0xB900 284 #define IO_INFO1_DAC1_OUT 0x0000 285 #define IO_INFO1_DAC2_OUT 0x0002 286 #define IO_INFO1_DAC3_OUT 0x0004 287 #define IO_INFO1_DAC4_OUT 0x0006 288 #define IO_INFO1_IIS1_OUT 0x0008 289 #define IO_INFO1_SPDIF_OUT 0x000A 290 #define IO_INFO1_HDMI_OUT 0x000C 291 292 #define DSP2XboxAddr_IO_Info2 DSP2XboxAddr_IO_Info1 + 0x000E 293 #define IO_INFO2_MUL_CH1 0x0000 294 #define IO_INFO2_MUL_CH2 0x0002 295 #define IO_INFO2_MUL_CH3 0x0004 296 #define IO_INFO2_MUL_CH4 0x0006 297 #define IO_INFO2_RAW 0x0008 298 #define IO_INFO2_RAW_DELAY 0x000A 299 #define IO_INFO2_RAW_DELAY_SE 0x000C 300 #define IO_INFO2_SCART 0x000E 301 #define IO_INFO2_KTV 0x0010 302 #define IO_INFO2_MUL_CH6 0x0012 303 #define IO_INFO2_SPDIF_DATA 0x0014 304 #define IO_INFO2_RESERVED4 0x0016 305 #define IO_INFO2_SINTONE 0x0018 306 #define IO_INFO2_MUL_CH8 0x001A 307 #define IO_INFO2_GPA_FS 0x001C 308 #define IO_INFO2_GPB_FS 0x001D 309 #define IO_INFO2_GPC_FS 0x001E 310 #define IO_INFO2_ALSA_MODE 0x001F 311 312 313 /* common */ 314 #define DSP2XboxAddr_dec1_signal_energy (DSP2XboxAddr_IO_Info2 + 0x0020) // len 1 315 #define DSP2XboxAddr_pcmCapture_overflow (DSP2XboxAddr_IO_Info2 + 0x0021) // len 1 316 #define DSP2XboxAddr_pcmCapture_underflow (DSP2XboxAddr_IO_Info2 + 0x0022) // len 1 317 #define DSP2XboxAddr_pcmCapture_volume (DSP2XboxAddr_IO_Info2 + 0x0023) // len 1 318 #define DSP2XboxAddr_pcmCapture2_overflow (DSP2XboxAddr_IO_Info2 + 0x0024) // len 1 319 #define DSP2XboxAddr_pcmCapture2_underflow (DSP2XboxAddr_IO_Info2 + 0x0025) // len 1 320 #define DSP2XboxAddr_pcmCapture2_volume (DSP2XboxAddr_IO_Info2 + 0x0026) // len 1 321 #define DSP2XboxAddr_pcmCapture3_overflow (DSP2XboxAddr_IO_Info2 + 0x0027) // len 1 322 #define DSP2XboxAddr_pcmCapture3_underflow (DSP2XboxAddr_IO_Info2 + 0x0028) // len 1 323 #define DSP2XboxAddr_pcmCapture3_volume (DSP2XboxAddr_IO_Info2 + 0x0029) // len 1 324 #define DSP2XboxAddr_swDmaRdr_ctrlBase (DSP2XboxAddr_IO_Info2 + 0x002A) // len 11 325 326 #define DSP2XboxAddr_hdmi_npcm_lock (DSP2XboxAddr_IO_Info2 + 0x0035) // len 1 327 #define DSP2XboxAddr_hdmi_unstable_protect (DSP2XboxAddr_IO_Info2 + 0x0036) // len 1 328 #define DSP2XboxAddr_hdmi_unstable_threshold (DSP2XboxAddr_IO_Info2 + 0x0037) // len 1 329 #define DSP2XboxAddr_hdmi_decimation_mode_flag (DSP2XboxAddr_IO_Info2 + 0x0038) // len 2 330 331 #define DSP2XboxAddr_mips_crisis_flag (DSP2XboxAddr_IO_Info2 + 0x003A) // len 1 332 333 /* basic sound effect */ 334 #define DSP2XboxAddr_AvcSOffsetAddr (DSP2XboxAddr_IO_Info2 + 0x003B) // len 1 335 #define DSP2XboxAddr_KTV_XAGain (DSP2XboxAddr_IO_Info2 + 0x003C) // len 1 336 #define DSP2XboxAddr_KTV_XBGain (DSP2XboxAddr_IO_Info2 + 0x003D) // len 1 337 #define DSP2XboxAddr_Multi_Channel_VOL (DSP2XboxAddr_IO_Info2 + 0x003E) // len 1 338 #define DSP2XboxAddr_MixerGroup1_Ctrl_addr (DSP2XboxAddr_IO_Info2 + 0x003F) // len 1 339 #define DSP2Xboxaddr_MixerGroup2_Ctrl_addr (DSP2XboxAddr_IO_Info2 + 0x0040) // len 1 340 #define DSP2XboxAddr_sinetone_StartFreq_Addr (DSP2XboxAddr_IO_Info2 + 0x0041) // len 1 341 #define DSP2XboxAddr_sinetone_EndFreq_Addr (DSP2XboxAddr_IO_Info2 + 0x0042) // len 1 342 #define DSP2XboxAddr_sinetone_SweepStep_Addr (DSP2XboxAddr_IO_Info2 + 0x0043) // len 1 343 #define DSP2XboxAddr_sinetone_Duration_Addr (DSP2XboxAddr_IO_Info2 + 0x0044) // len 1 344 345 /******************************************************************** 346 * Decoder default setting 347 ********************************************************************/ 348 /* SIF DSP PM vars */ 349 /* 350 #define ADDR_gain_base_2 0x2521 //B860 351 #define ADDR_thr_base_2 0x2620 352 #define ADDR_pfir_base_2 0x2690 353 // for SIF BTSC DSP PM vars // 354 #define BTSC_COMPILE_OPTION_Addr_2 0x25F1 // len 1 355 #define BTSC_OUTPUT_GAIN_Addr_2 0x2621 // len 2 356 #define BTSC_THRESHOLD_Addr_2 0x2623 // len 10 357 #define MTS_OUTPUT_GAIN_Addr_2 0x2634 //len 6 358 #define SIF_AGC_THRESHOLD_Addr_2 0x252D //len 3 359 360 /// PAL gain setting address 361 #define ADDR_fm_stdM_gain_2 ADDR_gain_base_2 // len = 4 362 #define ADDR_fm_stdX_gain_2 ADDR_fm_stdM_gain_2+4 // len = 4 363 #define ADDR_nicam_gain_2 ADDR_fm_stdX_gain_2+4 // len = 2 364 #define ADDR_am_gain_2 ADDR_nicam_gain_2+2 // len = 2 365 #define ADDR_agc_gain_2 ADDR_am_gain_2+2 // len = 24 366 367 // PAL threshold setting address 368 #define ADDR_a2_stdM_thr_2 ADDR_thr_base_2 // len = 15 369 #define ADDR_a2_stdBG_thr_2 ADDR_a2_stdM_thr_2+15 // len = 15 370 #define ADDR_a2_stdDK_thr_2 ADDR_a2_stdBG_thr_2+15 // len = 15 371 #define ADDR_a2_stdI_thr_2 ADDR_a2_stdDK_thr_2+15 // len = 4 372 #define ADDR_am_thr_2 ADDR_a2_stdI_thr_2+4 // len = 3 373 #define ADDR_hidev_stdM_thr_2 ADDR_am_thr_2+3 // len = 4 374 #define ADDR_hidev_stdBG_thr_2 ADDR_hidev_stdM_thr_2+4 // len = 4 375 #define ADDR_hidev_stdDK_thr_2 ADDR_hidev_stdBG_thr_2+4 // len = 4 376 #define ADDR_hidev_stdI_thr_2 ADDR_hidev_stdDK_thr_2+4 // len = 4 377 #define ADDR_nicam_stdBG_pherr_thr_2 ADDR_hidev_stdI_thr_2+4 //len = 3 378 #define ADDR_nicam_stdI_pherr_thr_2 ADDR_nicam_stdBG_pherr_thr_2+3 // len = 3 379 #define ADDR_a2_bg_nicam_fm_nsr_thr_2 0x246F // len = 1 380 #define ADDR_a2_dk_nicam_fm_nsr_thr_2 0x2470 // len = 1 381 382 // pfir setting address 383 #define ADDR_hidev_demfir_2 ADDR_pfir_base_2 // len = 15 384 #define ADDR_fm_ch1_pfir_2 ADDR_hidev_demfir_2+16 // len = 30 385 #define ADDR_fm_ch2_pfir_2 ADDR_fm_ch1_pfir_2+30 // len = 30 386 #define ADDR_hidev_lv1_pfir_2 ADDR_fm_ch2_pfir_2+30 // len = 20 387 #define ADDR_hidev_lv2_pfir_2 ADDR_hidev_lv1_pfir_2+20 // len = 20 388 #define ADDR_hidev_lv3_pfir_2 ADDR_hidev_lv2_pfir_2+20 // len = 20 389 390 // BTSC threshold setting address 391 #define HIDEV_NSR_THRESHOLD_Addr_2 BTSC_THRESHOLD_Addr_2+10 // len 2 392 #define BTSC_MONO_AMP_THRESHOLD_Addr_2 HIDEV_NSR_THRESHOLD_Addr_2+2 // len 2 393 #define HIDEV_AMP_THRESHOLD_Addr_2 BTSC_MONO_AMP_THRESHOLD_Addr_2+2 // len 2 394 395 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr_2 HIDEV_AMP_THRESHOLD_Addr_2+2 // len 1 396 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2 MTS_OUTPUT_GAIN_Addr_2+6 // len 3 397 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr_2 BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2+3 // len 1 398 */ 399 400 /************************************************ 401 * Below is MailBox config 402 *************************************************/ 403 404 /************************************************ 405 * MCU to DSP mailbox 406 ************************************************/ 407 /* SIF */ 408 #define M2S_MBOX_SIF_CMD_STANDARD MB_2DC0 409 #define M2S_MBOX_SIF_CMD_PFIRBANDWIDTH MB_2DC2 410 #define M2S_MBOX_SIF_CMD_MODE1 MB_2DC4 411 #define M2S_MBOX_SIF_CMD_MODE2 MB_2DC6 412 413 /* ATV Encoder */ 414 #define M2S_MBOX_ATVEnc_MODE_CTRL MB_2DC0 415 416 /* SPDIF */ 417 #define M2S_MBOX_SPDIF_SETTING MB_2D8E 418 #define M2S_MBOX_HDMI_SETTING MB_2D8E 419 #define MBOX_SPDIF_SETTING_BIT_MUTE MBOX_BIT0 420 #define MBOX_SPDIF_SETTING_BIT_NPCMSEL MBOX_BIT1 421 #define MBOX_SPDIF_SETTING_R2_NPCM_SELBIT MBOX_BIT2 422 #define MBOX_SPDIF_SETTING_DVB2_NPCM_SELBIT MBOX_BIT3 423 #define MBOX_SPDIF_SETTING_MINUS_11DB_BIT MBOX_BIT5 424 #define MBOX_HDMI_SETTING_BIT_NPCMSEL MBOX_BIT13 425 #define MBOX_HDMI_SETTING_BIT_HDMI_OUTPATH MBOX_BIT14 426 #define MBOX_HDMI_SETTING_BIT_MUTE MBOX_BIT15 427 428 #define M2S_MBOX_DOLBY_LOUDNESS_INFO MB_2D98 429 #define MBOX_DOLBY_LOUDNESS_ENABLE_BIT MBOX_BIT15 430 #define MBOX_DOLBY_LOUDNESS_ATSC_MODE MBOX_BIT14 431 #define MBOX_DOLBY_LOUDNESS_OTHER_MODE MBOX_BIT13 432 433 /* Sound effect */ 434 #define M2S_MBOX_AUOUT0_VOL MB_2D00 435 #define M2S_MBOX_AUOUT1_VOL MB_2D02 436 #define M2S_MBOX_AUOUT2_VOL MB_2D04 437 #define M2S_MBOX_AUOUT3_VOL MB_2D06 438 #define M2S_MBOX_I2S_VOL MB_2D08 439 #define M2S_MBOX_SPDIF_VOL MB_2D0A 440 #define M2S_MBOX_SRC_VOL MB_2D0C 441 #define M2S_MBOX_HDMI_VOL MB_2D0E //STB only 442 #define M2S_MBOX_I2S2_VOL MB_2D0E 443 #define M2S_MBOX_PRESCALE MB_2D10 444 445 #define M2S_MBOX_EQ1_GAIN MB_2D14 //[15:8] 446 #define M2S_MBOX_BASS_CTRL MB_2D14 //[7:0] 447 #define M2S_MBOX_EQ2_GAIN MB_2D16 //[15:8] 448 #define M2S_MBOX_TREBLE_CTRL MB_2D16 //[7:0] 449 #define M2S_MBOX_EQ3_GAIN MB_2D18 //[15:8] 450 #define M2S_MBOX_SUPBASS_CTRL MB_2D18 //[7:0] 451 #define M2S_MBOX_EQ4_GAIN MB_2D1A //[15:8] 452 #define M2S_MBOX_EQ5_GAIN MB_2D1C //[15:8] 453 #define M2S_MBOX_BAL_CTRL MB_2D1E 454 455 #define M2S_MBOX_SNDEFF_EN MB_2D20 456 #define M2S_MBOX_STEREO_EN_BIT MBOX_BIT15 457 #define M2S_MBOX_DRC_EN_BIT MBOX_BIT13 458 #define M2S_MBOX_AVC_EN_BIT MBOX_BIT12 459 #define M2S_MBOX_TONE_EN_BIT MBOX_BIT11 460 #define M2S_MBOX_SPATIAL_EN_BIT MBOX_BIT10 461 #define M2S_MBOX_VOLBAL_EN_BIT MBOX_BIT9 462 #define M2S_MBOX_GEQ_EN_BIT MBOX_BIT7 463 #define M2S_MBOX_EASE_EN_BIT MBOX_BIT6 464 #define M2S_MBOX_BASSBOOST_EN_BIT MBOX_BIT5 465 #define M2S_MBOX_ECHO_EN_BIT MBOX_BIT4 466 #define M2S_MBOX_DC_REMOVE_EN_BIT MBOX_BIT3 467 #define M2S_MBOX_HPF_EN_BIT MBOX_BIT2 468 #define M2S_MBOX_COEFFUPDATE_EN_BIT MBOX_BIT1 469 #define M2S_MBOX_PEQ_EN_BIT MBOX_BIT0 470 471 #define M2S_MBOX_VOLUME_EN MB_2D22 472 #define M2S_MBOX_VOL_DAC0_EN_BIT MBOX_BIT0 473 #define M2S_MBOX_VOL_DAC1_EN_BIT MBOX_BIT1 474 #define M2S_MBOX_VOL_DAC2_EN_BIT MBOX_BIT2 475 #define M2S_MBOX_VOL_DAC3_EN_BIT MBOX_BIT3 476 #define M2S_MBOX_VOL_I2S0_EN_BIT MBOX_BIT4 477 #define M2S_MBOX_VOL_I2S1_EN_BIT MBOX_BIT5 478 #define M2S_MBOX_VOL_I2S2_EN_BIT MBOX_BIT6 479 #define M2S_MBOX_VOL_I2S3_EN_BIT MBOX_BIT7 480 #define M2S_MBOX_VOL_SPDIF_EN_BIT MBOX_BIT8 481 #define M2S_MBOX_VOL_SRC_EN_BIT MBOX_BIT9 482 483 #define M2S_MBOX_AVC_CTRL MB_2D24 //[15:13] AT, [12:10] RT, [9:8] AVC_Mode, [7:0] AVC Threshold 484 #define M2S_MBOX_SURR_CTRL MB_2D26 485 486 #define M2S_MBOX_SINE_GEN MB_2D28 487 #define M2S_MBOX_SINE_GEN_CTRL_MASK 0x7F 488 #define M2S_MBOX_SINE_GEN_EN_BIT MBOX_BIT7 489 #define M2S_MBOX_MENUSOUND_MODE_SEL_MASK 0xF0 // [7:4] MENUSOUND Mode_Select, 0: Sine tone (default 1khz), 1: Sweep, 2: Sweep_300_800_5sec, 3: Sweep_800_300_5sec 490 #define M2S_MBOX_MENUSOUND_MUTE_RIGHT_BIT MBOX_BIT3 // [3] MENUSOUND RIGHT_CHANNEL_MUTE, 1->mute, 0->un-mute 491 #define M2S_MBOX_MENUSOUND_MUTE_LEFT_BIT MBOX_BIT2 // [2] MENUSOUND LEFT_CHANNEL_MUTE , 1->mute, 0->un-mute 492 #define M2S_MBOX_MENUSOUND_PAUSE_BIT MBOX_BIT1 // [1] MENUSOUND PAUSE 493 #define M2S_MBOX_MENUSOUND_PLAY_BIT MBOX_BIT0 // [0] MENUSOUND PLAY Trigger bit when change (from 0 to 1) 494 495 #define M2S_MBOX_BALANCE_EN MB_2D2A 496 #define M2S_MBOX_BAL_DAC0_EN_BIT MBOX_BIT0 497 #define M2S_MBOX_BAL_DAC1_EN_BIT MBOX_BIT1 498 #define M2S_MBOX_BAL_DAC2_EN_BIT MBOX_BIT2 499 #define M2S_MBOX_BAL_DAC3_EN_BIT MBOX_BIT3 500 #define M2S_MBOX_BAL_I2S0_EN_BIT MBOX_BIT4 501 #define M2S_MBOX_BAL_I2S1_EN_BIT MBOX_BIT5 502 #define M2S_MBOX_BAL_I2S2_EN_BIT MBOX_BIT6 503 #define M2S_MBOX_BAL_I2S3_EN_BIT MBOX_BIT7 504 #define M2S_MBOX_BAL_SPDIF_EN_BIT MBOX_BIT8 505 #define M2S_MBOX_BAL_SRC_EN_BIT MBOX_BIT9 506 #define M2S_MBOX_BAL_HDMI_EN_BIT MBOX_BIT10 507 508 #define M2S_MBOX_DRC_CTRL MB_2D2E //[7:0] DRC1 Threshold 509 #define M2S_MBOX_SOUND_MODE_SEL MB_2D30 //[1:0] : LR / LL / RR 510 #define M2S_MBOX_POWER_DOWN MB_2D30 //[8:9] 511 #define M2S_MBOX_NR_CTRL MB_2D32 512 513 #define M2S_MBOX_ADVSND_EN MB_2D40 514 #define M2S_MBOX_ADVSND_SUMMARY_EN_BIT MBOX_BIT15 515 516 #define M2S_MBOX_KTV_CTRL MB_2D46 517 #define M2S_MBOX_KTV_EN_BIT MBOX_BIT15 518 519 #define M2S_MBOX_INPUT_MUX_SEL1 MB_2D50 520 #define M2S_MBOX_INPUT_MUX_SEL2 MB_2D52 521 #define M2S_MBOX_INPUT_MUX_SEL3 MB_2D54 522 523 #define M2S_MBOX_KTV8_VOL MB_2D5A 524 #define M2S_MBOX_KTV5_VOL MB_2D5C 525 #define M2S_MBOX_KTV6_VOL MB_2D5E 526 #define M2S_MBOX_CH7_VOL MB_2D58 527 528 #define M2S_MBOX_AD_CONTROL MB_2DD8 529 #define M2S_MBOX_MIX_MODE_BSTART MBOX_BITS_SHIFT-11 530 #define M2S_MBOX_MIX_MODE_BMASK 0x7 531 532 /* M2S_MBOX_MIX_MODE */ 533 #define GPA_MIX_MODE_IS_FORWARD 0 534 #define GPA_MIX_MODE_IS_BACKWARD 1 535 #define GPA_MIX_MODE_IS_NULL 2 ! 2 & 3: NULL_Mixer_Mode 536 537 #define M2S_MBOX_DBG_CMD1 MB_2DDC 538 #define MBOX_DBGCMD_SET_ADDR 0x0200 539 #define MBOX_DBGCMD_WRITE_DM 0x0300 540 #define MBOX_DBGCMD_WRITE_PM 0x0400 541 #define MBOX_DBGCMD_READ_DM 0x0500 542 #define MBOX_DBGCMD_READ_PM 0x0600 543 #define MBOX_DBGCMD_READ_PMASK 0x0700 544 #define MBOX_DBGCMD_READ_IMASK 0x0800 545 546 #define MBOX_DBGCMD_READ_MAIN_VER 0x9000 547 #define MBOX_DBGCMD_READ_ALG1_VER 0x9100 548 #define MBOX_DBGCMD_READ_ALG2_VER 0x9200 549 550 //#define MBOX_DBGCMD_MIP_INT 0xE000 551 //#define MBOX_DBGCMD_ENC_INT 0xE100 552 //#define MBOX_DBGCMD_FILE_PTS_INT 0xEA00 553 554 #define MBOX_DBGCMD_RELOAD_SIF_BEG 0xF000 555 #define MBOX_DBGCMD_RELOAD_SIF_END 0xF100 556 #define MBOX_DBGCMD_WAIT_MCU_START 0xF300 557 #define MBOX_DBGCMD_RELOAD_ADVSND_BEG 0xF400 558 #define MBOX_DBGCMD_RELOAD_ADVSND_END 0xF500 559 560 #define M2S_MBOX_DBG_CMD2 MB_2DDE 561 562 /* MISC */ 563 #define M2S_MBOX_SW_DMA_READER_DDR_WtPtr MB_2D34 564 #define M2S_MBOX_SW_DMA_READER_DDR_Ctrl MB_2D36 565 #define M2S_MBOX_SW_DMA_READER_DDR_SynthFreq MB_2D56 566 #define M2S_MBOX_SW_DMA_READER_DDR_SynthFreq_L 0 //Reserved 567 568 #define M2S_MBOX_CAPTURE_CTRL MB_2D4A //[7:0] PCM_capture1 [15:8] PCM_capture2 569 //#define M2S_MBOX_CAPTURE3_CTRL //MB_2D4C //[7:0] PCM_capture3 //RESERVED 570 #define M2S_MBOX_GET_CH5 1 571 #define M2S_MBOX_GET_CH6 2 572 #define M2S_MBOX_GET_CH7 3 573 #define M2S_MBOX_GET_CH8 4 574 #define M2S_MBOX_GET_ADC1 5 575 #define M2S_MBOX_GET_ADC2 6 576 #define M2S_MBOX_GET_Raw_Delay_SE 7 577 #define M2S_MBOX_GET_MIXER 8 578 #define M2S_MBOX_GET_Raw 9 579 #define M2S_MBOX_GET_DEBUG 128 580 581 #define M2S_MBOX_PCM_CAPTURE_DDR_RdPtr MB_2DD4 582 #define M2S_MBOX_PCM_CAPTURE_DDR_Size MB_2DD6 583 584 #define M2S_MBOX_PCM_CAPTURE2_DDR_RdPtr MB_2D38 585 #define M2S_MBOX_PCM_CAPTURE2_DDR_Size MB_2D3A 586 587 //#define M2S_MBOX_PCM_CAPTURE3_DDR_RdPtr //MB_2D94 //RESERVED 588 //#define M2S_MBOX_PCM_CAPTURE3_DDR_Size //MB_2D96 //RESERVED 589 590 /************************************************ 591 * DSP to MCU mailbox 592 ************************************************/ 593 #define S2M_MBOX_ES_MEMCNT MB_2D70 594 #define S2M_MBOX_PCM_MEMCNT MB_2D72 595 #define S2M_MBOX_MM_BROWSE_TIME MB_2D74 596 #define S2M_MBOX_MM_PTS_IN_SEC MB_2D76 597 #define S2M_MBOX_MM_PTS_IN_MSEC MB_2D78 598 #define S2M_MBOX_MM_PTS_HI MB_2D7A 599 #define S2M_MBOX_MM_PTS_ME MB_2D7C 600 #define S2M_MBOX_MM_PTS_LO MB_2D7E 601 602 #define S2M_MBOX_DEC_STATUS MB_2DFA 603 604 #define S2M_MBOX_SIF_DETECTION_RESULT MB_2DE0 605 #define S2M_MBOX_SIF_STATUS_INFO MB_2DE2 606 #define S2M_MBOX_SIF_STATUS_MODE1 MB_2DE4 607 #define S2M_MBOX_SIF_STATUS_MODE2 MB_2DE6 608 #define S2M_MBOX_SIF_STATUS_NICAM_INFO MB_2DE8 609 #define S2M_MBOX_SIF_STATUS_NICAM_PARITY_ERR_CNT MB_2DEA 610 611 #define S2M_MBOX_NR_STATUS MB_2DEE 612 #define S2M_MBOX_BSND_STATUS MB_2DEE 613 #define MBOX_NR_WORKING_NOW MBOX_BIT0 // 1: NR working now , 0 NR not working 614 #define MBOX_TONE_FUNC_SELECT MBOX_BIT1 // 0: EQ_Bass_Treble , 1: Bass_Treble_old 615 #define MBOX_PEQ_FUNC_SELECT MBOX_BIT2 // 0: PEQ: single precision , 1: double precision 616 617 #define S2M_MBOX_MAIN_OVERFLOW_CNT MB_2DF2 //[15:8], full cnt of input SRAM buff2 618 #define S2M_MBOX_MAIN_UNDERFLOW_CNT MB_2DF2 //[ 7:0], empty cnt of output SRAM buff1 619 620 #define S2M_MBOX_ISR_CNTR MB_2DF6 //[15:8] 621 #define S2M_MBOX_INTR_CMDTYPE MB_2DF6 //[ 7:0] 622 #define SE_DSP_INTR_CMD_MMES_NEED_DATA 0x0300 623 #define SE_DSP_INTR_CMD_REPORT_PTS 0x0500 624 #define SE_DSP_INTR_CMD_MMUNI_NEED_DATA 0x0600 625 #define SE_DSP_INTR_CMD_VOIP 0x0900 626 #define DSP_INTR_CMD_PCM_UPLOAD 0x3300 627 #define DSP_INTR_CMD_PCM_DOWNLOAD 0xC000 628 629 #define S2M_MBOX_WHILE1_CNTR MB_2DF8 //[ 7:0] Always in Low Byte 630 #define S2M_MBOX_TIMER_CNTR MB_2DF8 //[15:8] Always in High Byte 631 632 #define S2M_MBOX_DBG_RESULT1 MB_2DFC // 633 #define S2M_MBOX_DSP_INIT_ACK 0x00E3 634 635 #define S2M_MBOX_DBG_RESULT2 MB_2DFE // 636 #define MBOX_DSP_RELOAD_ACK1 0x0033 637 #define MBOX_DSP_RELOAD_ACK2 0x0077 638 639 #define S2M_MBOX_SW_DMA_READER_DDR_Level MB_2DE0 640 641 #define S2M_MBOX_PCM_CAPTURE_DDR_WrPtr MB_2DF0 642 #define S2M_MBOX_PCM_CAPTURE2_DDR_WrPtr MB_2DF4 643 //#define S2M_MBOX_PCM_CAPTURE3_DDR_WrPtr //MB_2D7E //RESERVED 644 645 #ifdef _COMPILE_DSP_ 646 /************************************************ 647 * DSP ddr address mapping 648 *************************************************/ 649 /* DRAM Config */ 650 .const DSP2_TO_COMMON_DRAM_OFFSET = (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE); 651 652 /* SPDIF delay (GP C Bffer) */ 653 .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); 654 .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 655 656 /* HDMI delay (GP C Bffer) */ 657 .const HDMI_DLY_DRAM_BASE = (SE_HDMI_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); 658 .const HDMI_DLY_DRAM_SIZE = (SE_HDMI_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 659 660 /* sound system */ 661 .const DSP2_DMA_START_DRAM_BASE1 = (OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE); 662 .const DSP2_DMA_START_DRAM_SIZE1 = (SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE); 663 .const DSP2_DMA_START_DRAM_BASE2 = (OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE); 664 .const DSP2_DMA_START_DRAM_SIZE2 = (SE_MAIN_OUT_DRAM_SIZE / BYTES_IN_MIU_LINE); 665 666 /* Surround */ 667 #if(MSTAR_SURROUND_DRAM_SIZE>0) 668 #define SUR_DRAM_BASEADDR (OFFSET_MSTAR_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) // Line Address 669 #define SUR_DRAM_ENDADDR ((OFFSET_MSTAR_SURROUND_DRAM_ADDR + 0x0007E00) / BYTES_IN_MIU_LINE) // ((OFFSET_MSTAR_SURROUND_DRAM_ADDR + MSTAR_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line Address 670 #endif 671 672 /* HE-AAC Metadata Buffer on DEC */ 673 .const DSP2_HEAAC_METADATA_DRAM_BASE = (OFFSET_DDENC_METADATA_DRAM_ADDR / BYTES_IN_MIU_LINE); 674 .const DSP2_HEAAC_METADATA_DRAM_SIZE = (DDENC_METADATA_DRAM_SIZE / BYTES_IN_MIU_LINE); // 8KB 675 676 /* KTV */ 677 #if(KTV_SURROUND_DRAM_SIZE>0) 678 #define SUR_DRAM_KTV_BASEADDR (OFFSET_KTV_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) // Line address, Only in KTV mode, MS surround -> echo 679 #define SUR_DARM_KTV_ENDADDR ((OFFSET_KTV_SURROUND_DRAM_ADDR + 0x0001FE00) / BYTES_IN_MIU_LINE) //((OFFSET_KTV_SURROUND_DRAM_ADDR + KTV_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line address, Overlay with DM prefetch 680 #endif 681 682 /* DSP DM Prefetch */ 683 #define DSP2_DM_PREFETCH_DRAM_BASE (OFFSET_DM_PREFETCH_DRAM_ADDR / BYTES_IN_MIU_LINE) 684 #define DSP2_DM_PREFETCH_DRAM_SIZE (DM_PREFETCH_DRAM_SIZE / BYTES_IN_MIU_LINE) // 64KB 685 686 /* standalone DDCO PCM Buffer */ 687 //#define DSP2_DDE_PCM_DRAM_BASE (DSP2_DM_PREFETCH_DRAM_BASE+0x400) // AC3 Encode base address 688 //#define DSP2_DDE_PCM_DRAM_SIZE (0xBFF) // 48KB 689 .const DSP2_DDE_PCM_DRAM_BASE = (OFFSET_SER2_DDENC_MCHOUT_DRAM_ADDR / BYTES_IN_MIU_LINE); // AC3 Encode base address 690 .const DSP2_DDE_PCM_DRAM_SIZE = ((SER2_DDENC_MCHOUT_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); // 54kB 691 692 /* HEAD PHONE delay */ 693 #if(HEAD_PHONE_DLY_DRAM_SIZE>0) 694 .const DSP2_HEAD_PHONE_DLY_DRAM_BASE = (OFFSET_HEAD_PHONE_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 695 .const DSP2_HEAD_PHONE_DLY_DRAM_SIZE = ((HEAD_PHONE_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 696 #endif 697 698 /* CH5 input delay */ 699 #if(CH5_INPUT_DLY_DRAM_SIZE>0) 700 .const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 701 .const DSP2_CH5_INPUT_DLY_DRAM_SIZE = ((CH5_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 702 #endif 703 704 /* CH6 input delay */ 705 #if(CH6_INPUT_DLY_DRAM_SIZE>0) 706 .const DSP2_CH6_INPUT_DLY_DRAM_BASE = (OFFSET_CH6_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 707 .const DSP2_CH6_INPUT_DLY_DRAM_SIZE = ((CH6_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 708 #endif 709 710 /* multiChInput audio delay */ 711 #if(MULTI_CH_INPUT_DLY_DRAM_SIZE>0) 712 .const DSP2_MULTI_CH_INPUT_DLY_DRAM_BASE = (OFFSET_MULTI_CH_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 713 .const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 714 #endif 715 716 /* SPDIF Non-PCM */ 717 .const DSP2_SPDIF_DRAM_BASE = OFFSET_SPDIF_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE; 718 .const DSP2_SPDIF_DRAM_SIZE = (SPDIF_NONPCM_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 719 720 /* HDMI Non-PCM */ 721 .const DSP2_HDMI_DRAM_BASE = OFFSET_HDMI_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE; 722 .const DSP2_HDMI_DRAM_SIZE = (HDMI_NONPCM_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 723 724 /* pcmR_dmxPcm from preAsndR2 */ 725 .const DSP2_PCMR_DMXPCM_DRAM_BASE = (OFFSET_SER2_OUTPCM_DMX_DRAM_ADDR / BYTES_IN_MIU_LINE); 726 .const DSP2_PCMR_DMXPCM_DRAM_SIZE = ((SER2_OUTPCM_DMX_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 727 728 /* COMMON DRAM */ 729 730 /* PCM 1 / 2 */ 731 .const DSP2_PCM1_DRAM_BASE = (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM1_DRAM_ADDR / BYTES_IN_MIU_LINE)); 732 .const DSP2_PCM1_DRAM_SIZE = (PCM1_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 733 734 .const DSP2_PCM2_DRAM_BASE = (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM2_DRAM_ADDR / BYTES_IN_MIU_LINE)); 735 .const DSP2_PCM2_DRAM_SIZE = (PCM2_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 736 737 /* Software DMA */ 738 #if(SW_DMA_READER_DRAM_SIZE>0) 739 .const DSP2_SW_DMA_READER_DRAM_BASE = (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_SW_DMA_READER_DRAM_BASE / BYTES_IN_MIU_LINE)); 740 .const DSP2_SW_DMA_READER_DRAM_SIZE = ((SW_DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 741 #endif 742 /* PCM capture buffer */ 743 #if(PCM_CAPTURE_BUFFER_DRAM_SIZE>0) 744 .const DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE1_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 745 .const DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE = (PCM_CAPTURE_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE); 746 #endif 747 #if(PCM_CAPTURE2_BUFFER_DRAM_SIZE>0) 748 .const DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE2_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 749 .const DSP2_PCM_CAPTURE2_BUFFER_DRAM_SIZE = (PCM_CAPTURE2_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE); 750 #endif 751 #if(PCM_CAPTURE3_BUFFER_DRAM_SIZE>0) 752 .const DSP2_PCM_CAPTURE3_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE3_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 753 .const DSP2_PCM_CAPTURE3_BUFFER_DRAM_SIZE = (PCM_CAPTURE3_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE); 754 #endif 755 #define DSP2_PCM_CAPTURE_COPY_WORDSIZE 32 756 #define DSP2_PCM_CAPTURE_COPY_LINESIZE 4 757 758 /************************************************ 759 * DSP TSCALE & TCOUNT setting 760 ************************************************/ 761 #define DSP_SYSTEM_FREQUENCY 368 762 #define TSCALE_CONSTANT 0xF9 763 #define DSP_TIME_CONSTANT (DSP_SYSTEM_FREQUENCY/2 -1) 764 #define DSP_TIMER_SETTING DSP_TIME_CONSTANT 765 766 /************************************************ 767 * Below is DMA config 768 *************************************************/ 769 #define DMAITF_DSPCMD_ALIGNMENT_BIT 7 // 1/0 : msb / lsb alignment 770 #define DMAITF_DSPCMD_BYTESWAP_BIT 6 // set 1 to byte swap 771 #define DMAITF_DSPCMD_READY_BIT 5 // set 1 to trigger, will be 0 when dma is finished 772 #define DMAITF_DSPCMD_CLRCNTR_BIT 4 // set 1 to clear 773 #define DMAITF_DSPCMD_PRIORITY_BIT 3 // 1/0 : high / low 774 #define DMAITF_DSPCMD_24BITS_BIT 2 // 1/0 : 24bits / 16bits 775 776 #define DMAITF_DSPCMD_ALIGNMENT_MASK 0x80 777 #define DMAITF_DSPCMD_BYTESWAP_MASK 0x40 778 #define DMAITF_DSPCMD_READY_MASK 0x20 779 #define DMAITF_DSPCMD_CLRCNTR_MASK 0x10 780 #define DMAITF_DSPCMD_PRIORITY_MASK 0x08 781 #define DMAITF_DSPCMD_24BITS_MASK 0x04 782 #define DMAITF_DSPCMD_BURST_6 0x03 783 #define DMAITF_DSPCMD_BURST_3 0x02 784 #define DMAITF_DSPCMD_BURST_2 0x01 785 #define DMAITF_DSPCMD_BURST_1 0x00 786 787 #if (MIU_128 == 1) 788 /* 1 MIU Line = 128bit (16 bytes) */ 789 #define DMAITF_DSPWORDS_IN_1_LINE 8 790 #define DMAITF_DSPWORDS_IN_1LINE_LOG2 3 791 #define DMAITF_DSPWORDS_IN_3LINE_LOG2 4 792 #define DMAITF_WR_BIT 16 793 #define DMAITF_DM_BIT 15 794 #define DMAITF_BYTES_IN_1MIU_LINE BYTES_IN_MIU_LINE 795 796 #define DMAITF_RD_PM_MASK 0x000000 797 #define DMAITF_WR_PM_MASK 0x010000 798 #define DMAITF_RD_DM_MASK 0x008000 799 #define DMAITF_WR_DM_MASK 0x018000 800 801 #define DMAITF_16BITS_B1_DMA_CMD 0xA8 // 16 Bits Burst 1, high alignment 802 #define DMAITF_16BITS_B2_DMA_CMD 0xA8 //no Burst 2 cmd, use B1 instead 803 #define DMAITF_16BITS_B1_SWAP_DMA_CMD 0xE8 // 16 Bits Burst 1, high alignment 804 #define DMAITF_16BITS_B2_SWAP_DMA_CMD 0xE8 //no Burst 2 cmd, use B1 instead 805 806 #define DMAITF_24BITS_B3_DMA_CMD 0x2E // 24 Bits Burst 3 807 #define DMAITF_24BITS_B6_DMA_CMD 0x2E //no Burst 6 cmd, use B3 instead 808 809 #define DMAITF_16BITS_LowAlign_B1_DMA_CMD 0x28 //16 Bits Burst 1, low alignment 810 #define DMAITF_16BITS_LowAlign_B1_SWAP_DMA_CMD 0x68 //16 Bits Burst 1, low alignment 811 #else 812 /* 1 MIU Line = 64bit (8 bytes) */ 813 #define DMAITF_DSPWORDS_IN_1_LINE 4 814 #define DMAITF_DSPWORDS_IN_1LINE_LOG2 2 815 #define DMAITF_DSPWORDS_IN_3LINE_LOG2 3 816 #define DMAITF_WR_BIT 15 817 #define DMAITF_DM_BIT 14 818 #define DMAITF_BYTES_IN_1MIU_LINE BYTES_IN_MIU_LINE 819 820 #define DMAITF_RD_PM_MASK 0x000000 821 #define DMAITF_WR_PM_MASK 0x008000 822 #define DMAITF_RD_DM_MASK 0x004000 823 #define DMAITF_WR_DM_MASK 0x00C000 824 825 #define DMAITF_16BITS_B1_DMA_CMD 0xA8 // 16 Bits Burst 1, high alignment 826 #define DMAITF_16BITS_B2_DMA_CMD 0xA9 827 #define DMAITF_16BITS_B1_SWAP_DMA_CMD 0xE8 // 16 Bits Burst 1, high alignment 828 #define DMAITF_16BITS_B2_SWAP_DMA_CMD 0xE9 829 830 #define DMAITF_24BITS_B3_DMA_CMD 0x2E // 24 Bits Burst 3 831 #define DMAITF_24BITS_B6_DMA_CMD 0x2F // 24 Bits Burst 6 832 833 #define DMAITF_16BITS_LowAlign_B1_DMA_CMD 0x28 //16 Bits Burst 1, low alignment 834 #define DMAITF_16BITS_LowAlign_B1_SWAP_DMA_CMD 0x68 //16 Bits Burst 1, low alignment 835 #endif 836 837 /* DMA Mapping */ 838 #define General_DSP_IDMA_CMD_Number 15 // just info this chip nubmer of DSP_IDMA can support, (no any purpose) need sync with HW spec 839 840 #define SNDISR1_DMA_CTRL DSPDMA7_DMA_CTRL 841 #define SNDISR2_DMA_CTRL DSPDMA2_DMA_CTRL 842 #define SPDIF_DMA_CTRL DSPDMA6_DMA_CTRL // SPDIF npcm 843 #define HDMI_DMA_CTRL DSPDMA6_DMA_CTRL // HDMI npcm 844 #define PCM_CAPTURE_DMA_CTRL DSPDMA15_DMA_CTRL 845 #define PCM_CAPTURE2_DMA_CTRL DSPDMA14_DMA_CTRL 846 #define PCM_CAPTURE3_DMA_CTRL DSPDMA13_DMA_CTRL 847 #define SW_DMARDR_DMA_CTRL DSPDMA13_DMA_CTRL 848 #define HP_DLY_DMA_CTRL DSPDMA13_DMA_CTRL 849 #define CH5_IN_DLY_DMA_CTRL DSPDMA12_DMA_CTRL 850 #define CH6_IN_DLY_DMA_CTRL DSPDMA11_DMA_CTRL 851 #define MULTI_CH_INPUT_DLY_DMA_CTRL DSPDMA9_DMA_CTRL 852 #define R2_DEC_PCM1R_DMA_CTRL PCM1R_DMA_CTRL 853 #define DDE_ISR_PCM_DMA_CTRL DSPDMA1_DMA_CTRL 854 #define SPDIF_DLY_IN_DMA_CTRL DSPDMA2_DMA_CTRL 855 #define HDMI_DLY_IN_DMA_CTRL DSPDMA2_DMA_CTRL 856 #define SPDIF_DLY_OUT_DMA_CTRL DSPDMA6_DMA_CTRL 857 #define HDMI_DLY_OUT_DMA_CTRL DSPDMA6_DMA_CTRL 858 #define PCMR_DMXPCM_DMA_CTRL PCM1R_DMA_CTRL 859 860 #define SNDBG_DMA_CTRL DSPDMA3_DMA_CTRL // Background sound effect 861 #define ADEC_DMA1_CTRL DSPDMA3_DMA_CTRL 862 #define ADEC_DMA2_CTRL DSPDMA4_DMA_CTRL 863 #define ADEC_DMA3_CTRL DSPDMA3_DMA_CTRL 864 #define ADEC_DMA4_CTRL DSPDMA4_DMA_CTRL 865 #define ADEC_DMA5_CTRL DSPDMA5_DMA_CTRL 866 867 /************************************************ 868 * Below is DSP FIFO/DDR unit Setting 869 *************************************************/ 870 .const SE_R2_FRAME_SIZE = 256; //256 samples for R2_SE 871 .const SE_PROCESS_FRAME_SMP_UNIT = 128; //128 samples per frame 872 873 .const SE_PROCESS_FETCH_FRAME_LINE_SIZE = SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE; 874 .const SE_PROCESS_STORE_FRAME_LINE_SIZE = SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE; 875 876 /* sound effect buffer / share buffer setting */ 877 .const SE_PROCESS_FIFO_SIZE_UNIT = 64; //delay fifo size per channel 878 .const SE_PROCESS_DMA_WORD_SIZE_UNIT = 16; //DMA_WORD_SIZE per channel 879 880 /* input ISR PCM samples -> DDR1 unit setting */ 881 .const SE_BUFF2_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * SE_PROCESS_FETCH_CHANNELS); 882 .const SE_BUFF2_DMA_WORD_SIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * SE_PROCESS_FETCH_CHANNELS); // (DMA_WORD_SIZE per channel) * channel number 883 .const SE_BUFF2_DMA_24BIT_LINE_SIZE = SE_BUFF2_DMA_WORD_SIZE*3/BYTES_IN_MIU_LINE; 884 .const SE_BUFF2_DMA_16BIT_LINE_SIZE = SE_BUFF2_DMA_WORD_SIZE*2/BYTES_IN_MIU_LINE; 885 886 /* DDR2 --> output ISR PCM samples */ 887 .const SE_BUFF1_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * SE_PROCESS_STORE_CHANNELS); 888 .const SE_BUFF1_DMA_WORD_SIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * SE_PROCESS_STORE_CHANNELS); // (DMA_WORD_SIZE per channel) * channel number 889 .const SE_BUFF1_DMA_24BIT_LINE_SIZE = SE_BUFF1_DMA_WORD_SIZE*3/BYTES_IN_MIU_LINE; 890 .const SE_BUFF1_DMA_16BIT_LINE_SIZE = SE_BUFF1_DMA_WORD_SIZE*2/BYTES_IN_MIU_LINE; 891 892 /* share buffer in dm mapping */ 893 .const SE_PROCESS_BUFFER_MAIN = 0x0; 894 .const SE_PROCESS_BUFFER_MAIN_RAW1_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*0; 895 .const SE_PROCESS_BUFFER_MAIN_RAW2_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*2; 896 .const SE_PROCESS_BUFFER_MAIN_SE_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*4; 897 .const SE_PROCESS_BUFFER_MAIN_SE_LmRm = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*6; 898 .const SURR_DLY_BUFFER = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*8; 899 .const NR_PARAMETER_BUFFER = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*10; 900 .const SE_PROCESS_BUFFER_MAIN_TMP = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*12; //0x600 901 902 #define DSP2DmAddr_system_shareBuff 0x0 //SE_PROCESS_BUFFER_MAIN 903 #define DSP2DmAddr_system_shareBuff_size (0x600) //(SE_PROCESS_BUFFER_MAIN_TMP - SE_PROCESS_BUFFER_MAIN) 904 #define DSP2DmAddr_advSnd_shareBuff_base SE_PROCESS_BUFFER_MAIN_TMP 905 #define DSP2DmAddr_advSnd_shareBuff_size (0x1500) // min size: (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS) for system frame base SE 906 907 .const SndEff_Array_TMP1 = SE_PROCESS_BUFFER_MAIN_TMP; 908 .const SndEff_Array_TMP2 = SndEff_Array_TMP1 + SE_PROCESS_FRAME_SMP_UNIT*2; 909 .const SndEff_Array_TMP3 = SndEff_Array_TMP2 + SE_PROCESS_FRAME_SMP_UNIT*2; 910 .const SndEff_Array_TMP4 = SndEff_Array_TMP3 + SE_PROCESS_FRAME_SMP_UNIT*2; 911 912 .const Apply_NR_Status_BUFFER = NR_PARAMETER_BUFFER; 913 .const Apply_NR_Gain_BUFFER = Apply_NR_Status_BUFFER + SE_PROCESS_FRAME_SMP_UNIT; 914 915 /* General delay buffer template */ 916 .const DELAY_FIFO_SIZE = 128; 917 .const DELAY_DMA_WORDSIZE = 32; 918 .const DELAY_DMA_LINESIZE = DELAY_DMA_WORDSIZE*3/BYTES_IN_MIU_LINE; 919 920 .const MULTI_CH_INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); // fifo len 921 .const MULTI_CH_INPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); 922 .const MULTI_CH_INPUT_DELAY_DMA_LINESIZE = (MULTI_CH_INPUT_DELAY_DMA_WORDSIZE*3/BYTES_IN_MIU_LINE); 923 924 /* Dly_status */ 925 .const DELAY_INPUT_STOP = 0; 926 .const DELAY_OUTPUT_STOP = 1; 927 .const DELAY_DLYIN_DMA_ASSERT = 2; 928 .const DELAY_DLYOUT_DMA_ASSERT = 3; 929 930 /* Mstar Surround delay buffer */ 931 .const SUR_FIFO_UNIT = SE_PROCESS_FRAME_SMP_UNIT*2; 932 .const SUR_DRAM_BURSRT = (SUR_FIFO_UNIT*3)/BYTES_IN_MIU_LINE; 933 934 /* spdif delay unit setting */ 935 .const SPDIF_DLYBUF_DMA_WORDSIZE = 32; 936 .const SPDIF_DLYBUF_DMA_LINESIZE = SPDIF_DLYBUF_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 937 .const SPDIF_DLYFIFO_LEN = 64; 938 939 /* spdif nonPcm unit setting */ 940 .const SPDIF_NPCM_DMA_WORDSIZE = 32; 941 .const SPDIF_NPCM_DMA_LINESIZE = SPDIF_NPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 942 .const SPDIF_NPCMFIFO_LEN = 64; 943 944 /* pcmR_dmxPcm unit setting */ 945 .const PCMR_DMXPCM_DMA_WORDSIZE = 32; 946 .const PCMR_DMXPCM_DMA_LINESIZE = PCMR_DMXPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 947 .const PCMR_DMXPCMFIFO_LEN = 64; 948 949 /* hdmi npcm fifo unit setting */ 950 .const HDMI_NPCM_DMA_WORDSIZE = 128; 951 .const HDMI_NPCM_DMA_LINESIZE = HDMI_NPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 952 .const HDMI_NFIFO_LEN = 128*2; 953 954 /* hdmi delay unit setting */ 955 .const HDMI_DLYBUF_DMA_WORDSIZE = 32; 956 .const HDMI_DLYBUF_DMA_LINESIZE = HDMI_DLYBUF_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 957 .const HDMI_DLYFIFO_LEN = 64; 958 959 /* SW DMA */ 960 .const SW_DMA_CTRL_RESET_BIT = 0; 961 .const SW_DMA_CTRL_START_BIT = 1; 962 .const SW_DMA_CTRL_CIRCL_BIT = 2; 963 964 .const SW_DMA_WORDSIZE = 32; 965 .const SW_DMA_LINESIZE = SW_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 966 967 /******************************************************************** 968 * DSP ISR mapping 969 ********************************************************************/ 970 /* default 0 (no use) */ 971 #define ISR_MASK_PCM IMASK_SP1T_IRQ1 972 #define ISR_MASK_PCM2 IMASK_SP1R_IRQ0 973 #define ISR_MASK_TIMER IMASK_TM 974 975 /* default -1 (no use) */ 976 #define ISR_PMASK_PCM -1 977 #define ISR_PMASK_PCM2 -1 978 #define ISR_PMASK_DEC_R2_CMD 2 //from R2_0 IO 0xB000_0860 979 #define ISR_PMASK_R2_LOAD_CODE_CMD 3 //from R2_0 IO 0xB000_0840 980 #define ISR_PMASK_SPDIF2_ISR 0 //no use 981 #define ISR_PMASK_HDMI_ISR IMASK_IRQL1 982 983 #define DEC_MAIN_FUNC_PTR g_DecFunPtr 984 #define PCMOUT_FUNC_PTR g_IRQ1_isr_funcPtr 985 #define SIF_PCMOUT_FUNC_PTR g_IRQ0_isr_funcPtr 986 #define SIF_ENC_FUNC_PTR g_SifEncFuncPtr 987 #define SIF_ENC_DATAOUT_FUNC_PTR g_SifEncDataOutFuncPtr 988 989 /******************************************************************** 990 * DSP internal mailbox mapping 991 ********************************************************************/ 992 993 /* SPDIF NonPCM */ 994 #define D2S_MBOX_SPDIF_CTRL ddco_spdifNpcmCtrl // [0:2]=Acmod for AC3/AC3+/HE-AAC, [3]=LFE flag, 995 // [ 8:11]: HDMI sample rate 996 // 0: 96K, 1: 88K, 2: 64K 997 // 3: 48K, 4: 44K, 5: 32K 998 // 6: 24K, 7: 22K, 8: 16K 999 // 9: 12K, a: 11K, b: 8K 1000 // c:192K, d: 176K e: 128K 1001 // [12:15]: SPDIF sample rate 1002 // 0: 96K, 1: 88K, 2: 64K 1003 // 3: 48K, 4: 44K, 5: 32K 1004 // 6: 24K, 7: 22K, 8: 16K 1005 // 9: 12K, a: 11K, b: 8K 1006 // [18] info to DDCO: 1-> -4.75dB; 0-> do nothing 1007 // [19] : 1->48KHz, 0->non-48KHz 1008 // [20] MultiCH_EN, [21]=ADEC Stop/Play,[22]=Freeze,[23]=Start 1009 #define D2S_MBOX_SPDIF_WRPTR ddco_spdifNpcmWrPtr 1010 #define S2D_MBOX_SPDIF_RDPTR ddco_spdifNpcmRdPtr 1011 1012 .const MBOX_MULTI_CHANNEL_ENABLE_BIT = 20; 1013 .const MBOX_SPDIF_NPCM_CTRL_BIT_PLAY = 17; 1014 .const MBOX_SPDIF_NPCM_CTRL_BIT_FREEZE = 22; 1015 .const MBOX_SPDIF_NPCM_CTRL_BIT_START = 19; 1016 .const MBOX_HDMI_NPCM_CTRL_BIT_PLAY = 21; 1017 .const MBOX_HDMI_NPCM_CTRL_BIT_START = 23; 1018 //[23] HDMI nonPcm Start 1019 //[22] 1020 //[21] HDMI nonPcm PlayEnable 1021 //[20] HDMI HBR mode 1022 //[19] SPDIF nonPcm Start 1023 //[18] inform DDEncode to attenuate 4.75dB 1024 //[17] SPDIF nonPcm PlayEnable 1025 //[16] 1026 //[15:12] SPDIF nonPcm sampleRate index 1027 // 0: 96K, 1: 88K, 2: 64K 1028 // 3: 48K, 4: 44K, 5: 32K 1029 // 6: 24K, 7: 22K, 8: 16K 1030 // 9: 12K, a: 11K, b: 8K 1031 1032 //[11:8] HDMI nonPcm sampleRate index 1033 // 0: 96K, 1: 88K, 2: 64K 1034 // 3: 48K, 4: 44K, 5: 32K 1035 // 6: 24K, 7: 22K, 8: 16K 1036 // 9: 12K, a: 11K, b: 8K 1037 // c:192K, d: 176K e: 128K 1038 1039 //[7] HDMI is Pcm or nonPcm 1040 //[6] SPDIF is Pcm or nonPcm 1041 //[5:4] hdmi nonPcm owner 1042 //[3:2] spdif nonPcm owner 1043 //[0:1] spdif/hdmi PCM attenuator index 1044 1045 #define NULL_PAYLOAD_TEST 1 1046 1047 #if (NULL_PAYLOAD_TEST == 1) 1048 .const SPDIF_NPCM_MUTE_FRMCNT = 0x8; 1049 .const SPDIF_PCM_MUTE_SMPCNT = 0; 1050 .const SPDIF_NPCM_NULL_FRMCNT = 0x0 + SPDIF_NPCM_MUTE_FRMCNT; 1051 #else 1052 .const SPDIF_NPCM_MUTE_FRMCNT = 0x10; 1053 .const SPDIF_PCM_MUTE_SMPCNT = 0; 1054 #endif 1055 1056 /* Mailbox with DEC R2 */ 1057 #define D2S_MBOX_LOAD_CODE_CMD DECR2M_2_DSP_MAILBOX0 1058 #define D2S_MBOX_PCMISR_CTRL DECR2M_2_DSP_MAILBOX1 1059 #define MBOX_R2_PCM1ISR_PLAY_START_BIT 0 //--> �o�U�� playSmpFlag / stop / pause �M�w 1060 #define MBOX_R2_PCM1ISR_PLAY_MUTE_BIT 1 //--> Mute 1061 #define MBOX_R2_PCM1ISR_USING_ASINK_ISR_BIT 2 1062 #define MBOX_R2_PCM2ISR_PLAY_START_BIT 8 1063 #define MBOX_R2_PCM2ISR_PLAY_MUTE_BIT 9 1064 #define MBOX_R2_PCM2ISR_USING_ASINK_ISR_BIT 10 1065 1066 #define D2S_MBOX_PCM1_DRAM_WRPTR DECR2M_2_DSP_MAILBOX2 1067 #define D2S_MBOX_PCM1_SYNTH_H DECR2M_2_DSP_MAILBOX3 1068 #define D2S_MBOX_PCM1_SYNTH_L DECR2M_2_DSP_MAILBOX4 1069 1070 #define D2S_MBOX_PCM2_DRAM_WRPTR DECR2M_2_DSP_MAILBOX5 1071 #define D2S_MBOX_PCM2_SYNTH_H DECR2M_2_DSP_MAILBOX6 1072 #define D2S_MBOX_PCM2_SYNTH_L DECR2M_2_DSP_MAILBOX7 1073 1074 #define D2S_MBOX_R2_TO_DSP_COMMAND DECR2M_2_DSP_MAILBOX8 1075 #define D2S_CMD_UPD_PCM1_MUTECNT 0x0001 // Bit0 1076 #define D2S_CMD_CLR_PCM1_PLAYCNT 0x0002 // Bit1 1077 #define D2S_CMD_UPD_PCM1_PLAYCNT 0x0004 // Bit2 1078 #define D2S_CMD_FLUSH_PCM1_SMPS 0x0008 // Bit3 1079 #define D2S_CMD_RESET_PCM1 0x0010 // Bit4 1080 #define D2S_CMD_UPD_PCM2_MUTECNT 0x0020 // Bit5 1081 #define D2S_CMD_CLR_PCM2_PLAYCNT 0x0040 // Bit6 1082 #define D2S_CMD_UPD_PCM2_PLAYCNT 0x0080 // Bit7 1083 #define D2S_CMD_FLUSH_PCM2_SMPS 0x0100 // Bit8 1084 #define D2S_CMD_RESET_PCM2 0x0200 // Bit9 1085 1086 #define D2S_MBOX_R2_TO_DSP_PARAM DECR2M_2_DSP_MAILBOX9 1087 #define D2S_R2_SPDIF_WR_PTR DECR2M_2_DSP_MAILBOXA 1088 #define D2S_MBOX_HDMI_NPCM_WRPTR DECR2M_2_DSP_MAILBOXB 1089 1090 #define D2S_MBOX_HDMI_NPCM_CMD DECR2M_2_DSP_MAILBOXC 1091 #define D2S_R2_SPDIF_CTRL DECR2M_2_DSP_MAILBOXC 1092 #define D2S_MBOX_NPCM_CTRL D2S_R2_SPDIF_CTRL 1093 //#define MBOX_HDMI_NPCM_CTRL_BIT_START MBOX_BIT23 1094 //#define MBOX_HDMI_NPCM_CTRL_BIT_PLAY MBOX_BIT21 1095 //#define MBOX_MULTI_CHANNEL_ENABLE_BIT MBOX_BIT20 1096 //#define MBOX_SPDIF_NPCM_CTRL_BIT_START MBOX_BIT19 1097 #define MBOX_SPDIF_NPCM_DDE_MINUS_4_75DB MBOX_BIT18 1098 //#define MBOX_SPDIF_NPCM_CTRL_BIT_PLAY MBOX_BIT17 1099 #define MBOX_HDMI_NONPCM_FROM_ASND_DSP_BIT MBOX_BIT5 1100 #define MBOX_HDMI_NONPCM_FROM_ASND_R2_BIT MBOX_BIT4 1101 #define MBOX_SPDIF_NONPCM_FROM_ASND_DSP_BIT MBOX_BIT3 1102 #define MBOX_SPDIF_NONPCM_FROM_ASND_R2_BIT MBOX_BIT2 1103 //[23] HDMI nonPcm Start 1104 //[22] 1105 //[21] HDMI nonPcm PlayEnable 1106 //[20] HDMI HBR mode 1107 //[19] SPDIF nonPcm Start 1108 //[18] inform DDEncode to attenuate 4.75dB 1109 //[17] SPDIF nonPcm PlayEnable 1110 //[16] 1111 //[15:12] SPDIF nonPcm sampleRate index 1112 // 0: 96K, 1: 88K, 2: 64K 1113 // 3: 48K, 4: 44K, 5: 32K 1114 // 6: 24K, 7: 22K, 8: 16K 1115 // 9: 12K, a: 11K, b: 8K 1116 1117 //[11:8] HDMI nonPcm sampleRate index 1118 // 0: 96K, 1: 88K, 2: 64K 1119 // 3: 48K, 4: 44K, 5: 32K 1120 // 6: 24K, 7: 22K, 8: 16K 1121 // 9: 12K, a: 11K, b: 8K 1122 // c:192K, d: 176K e: 128K 1123 1124 //[7] HDMI is Pcm or nonPcm 1125 //[6] SPDIF is Pcm or nonPcm 1126 //[5:4] hdmi nonPcm owner 1127 //[3:2] spdif nonPcm owner 1128 //[0:1] spdif/hdmi PCM attenuator index //Dolby Bulletin 11: PCM Level control, 0: 0dB, 1:-7dB(ATSC), 2:-8dB(DVB), 3:-11dB(ISDB) 1129 1130 #define D2S_R2_DOLBY_META_DATA DECR2M_2_DSP_MAILBOXD 1131 #define D2S_DSP_ENCODE_SETTING DECR2M_2_DSP_MAILBOXE 1132 #define MBOX_NONPCM_DDE_ENABLE_BIT MBOX_BIT6 1133 #define MBOX_NONPCM_DTSE_ENABLE_BIT MBOX_BIT5 1134 //[6] DSP DDENC ENABLE bit 1135 //[5] DSP DTS ENC ENABLE bit 1136 //[4] LFE 1137 //[3:0] AC mode 1138 1139 /************************************************************/ 1140 1141 #define S2D_MBOX_DSP_TO_R2_COMMAND DSP_2_DECR2M_MAILBOX0 1142 #define S2D_CMD_RESET_PCM1_AVSYNC 0x0001 1143 #define S2D_CMD_RESET_PCM2_AVSYNC 0x0002 1144 1145 #define S2D_MBOX_DSP_TO_R2_PARAM DSP_2_DECR2M_MAILBOX1 1146 #define S2D_MBOX_R2CMD_RECEIVE_CNT DSP_2_DECR2M_MAILBOX2 1147 1148 #define S2D_MBOX_PCM1_PLAYCNT DSP_2_DECR2M_MAILBOX3 1149 #define S2D_MBOX_PCM1_FIFOCNT DSP_2_DECR2M_MAILBOX4 1150 #define S2D_MBOX_PCM1_DRAM_RDPTR DSP_2_DECR2M_MAILBOX5 1151 1152 #define S2D_MBOX_PCM2_PLAYCNT DSP_2_DECR2M_MAILBOX6 1153 #define S2D_MBOX_PCM2_FIFOCNT DSP_2_DECR2M_MAILBOX7 1154 #define S2D_MBOX_PCM2_DRAM_RDPTR DSP_2_DECR2M_MAILBOX8 1155 1156 #define S2D_MBOX_ENCODE_SURPPORT DSP_2_DECR2M_MAILBOX9 1157 #define DDE_ENCODE_SURPPORT_BIT MBOX_BIT0 1158 #define DTSE_ENCODE_SURPPORT_BIT MBOX_BIT1 1159 #define DDPE_ENCODE_SURPPORT_BIT MBOX_BIT2 1160 1161 #define S2D_R2_SPDIF_RD_PTR DSP_2_DECR2M_MAILBOXA 1162 #define S2D_MBOX_HDMI_NPCM_RDPTR DSP_2_DECR2M_MAILBOXB 1163 1164 #define S2D_IP_SECURITY_KEY DSP_2_DECR2M_MAILBOXE 1165 #define S2D_OTP_BOUNDING DSP_2_DECR2M_MAILBOXF 1166 1167 #define S2A_IP_SECURITY_KEY DSP_2_SNDR2M_MAILBOXE 1168 #define S2A_OTP_BOUNDING DSP_2_SNDR2M_MAILBOXF 1169 1170 !#define S2A_R2_PCMIN_WRPTR DSP_2_DECR2M_MAILBOX7 1171 !#define S2A_R2_PCMIN2_WRPTR DSP_2_DECR2M_MAILBOX8 1172 !#define S2A_R2_SPDIF_RD_PTR DSP_2_DECR2M_MAILBOX9 1173 !#define S2A_IP_SECURITY_KEY DSP_2_DECR2M_MAILBOXE 1174 !#define S2A_OTP_BOUNDING DSP_2_DECR2M_MAILBOXF 1175 1176 !#define A2S_R2_PCMOUT_WRPTR DECR2M_2_DSP_MAILBOXD 1177 !#define A2S_R2_PCMOUT2_WRPTR DECR2M_2_DSP_MAILBOX0 1178 !#define A2S_R2_SPDIF_WR_PTR DECR2M_2_DSP_MAILBOXE 1179 !#define A2S_R2_SPDIF_CTRL DECR2M_2_DSP_MAILBOXF 1180 /* Mailbox with SND R2 */ 1181 #define S2A_R2_PCMIN_WRPTR DSP_2_SNDR2M_MAILBOX1 1182 #define S2A_R2_PCMIN2_WRPTR DSP_2_SNDR2M_MAILBOX2 1183 #define S2A_R2_SPDIF_RD_PTR DSP_2_SNDR2M_MAILBOX3 1184 #define S2A_IP_SECURITY_KEY DSP_2_SNDR2M_MAILBOXE 1185 #define S2A_OTP_BOUNDING DSP_2_SNDR2M_MAILBOXF 1186 #define S2A_MBOX_HDMI_NPCM_RDPTR DSP_2_SNDR2M_MAILBOX4 1187 #define S2A_MBOX_PCMR_DMXPCM_RDPTR DSP_2_SNDR2M_MAILBOX5 // pcmR_dmxPcm from preAsndR2 RDPTR 1188 #define S2A_MBOX_SPEAKER_CH_VOLUME DSP_2_SNDR2M_MAILBOXA 1189 1190 #define A2S_R2_PCMOUT_WRPTR SNDR2M_2_DSP_MAILBOX1 1191 #define A2S_R2_PCMOUT2_WRPTR SNDR2M_2_DSP_MAILBOX2 1192 #define A2S_R2_SPDIF_WR_PTR SNDR2M_2_DSP_MAILBOX3 1193 #define A2S_MBOX_HDMI_NPCM_WRPTR SNDR2M_2_DSP_MAILBOX4 1194 #define A2S_R2_SPDIF_CTRL SNDR2M_2_DSP_MAILBOX5 1195 #define A2S_MBOX_HDMI_NPCM_CMD SNDR2M_2_DSP_MAILBOX5 1196 #define A2S_R2_DOLBY_META_DATA SNDR2M_2_DSP_MAILBOX6 1197 #define A2S_MBOX_DDENC_OUTMCH_WRPTR SNDR2M_2_DSP_MAILBOX6 1198 1199 #define A2S_MBOX_R2_TO_DSP_CTRL SNDR2M_2_DSP_MAILBOX7 1200 #define A2S_DDENC_ENABLE MBOX_BIT0 1201 #define A2S_CMD_SOUND_MIXER_DISABLE_BIT MBOX_BIT1 //[1] SOUND_MIXER, 0:in DSP (MS11), 1:in SND_R2 (MS12) 1202 1203 #define A2S_MBOX_PCMR_DMXPCM_WRPTR SNDR2M_2_DSP_MAILBOX9 // pcmR_dmxPcm from preAsndR2 WRPTR 1204 1205 #define A2S_R2_SOUND_PROCESS_CTRL SNDR2M_2_DSP_MAILBOXF 1206 #define MBOX_PRE_SOUND_PROCESS_DISABLE_BIT MBOX_BIT0 1207 #define MBOX_POST_SOUND_PROCESS_DISABLE_BIT MBOX_BIT1 1208 1209 /******************************************************************** 1210 * DSP io mapping 1211 ********************************************************************/ 1212 #define NULL_IO 0 1213 1214 /* DSP common IO */ 1215 #define DSPIO_SPDIF_IN_FREQ STATUS_SPDIF_FREQ 1216 #define DSPIO_HDMI_IN_FREQ STATUS_HDMI_FREQ 1217 #define DSPIO_HDMI_IN_PC STATUS_HDMI_PC 1218 1219 /* DSP Bounding IO */ 1220 #define DSP_BOUND_OPTION 1 1221 #define DSPIO_BOUND_OPTION 0xA0FF 1222 .const BOUNDING_BIT_DD = 0; //DD 1223 .const BOUNDING_BIT_DDP = 1; //DD+ 1224 .const BOUNDING_BIT_DPULSE = 2; //Dolby Pulse (MS10 DDT) or DDCO 1225 .const BOUNDING_BIT_DVOL = 3; //Dolby Volume 1226 .const BOUNDING_BIT_DTRUEHD = 4; //Dolby TrueHD 1227 .const BOUNDING_BIT_DDDCO = 5; //Dolby DDCO 1228 .const BOUNDING_BIT_DTSENVELO = 6; //DTS Envelo / Symmetry 1229 .const BOUNDING_BIT_DTSDMP = 7; //DTS DMP 1230 .const BOUNDING_BIT_DTSLBR = 8; //DTS LBR 1231 .const BOUNDING_BIT_DTSTS = 9; //DTS Transcoder 1232 .const BOUNDING_BIT_DTSCORELESS = 10; //DTS Coreless 1233 .const BOUNDING_BIT_SRS = 11; //SRS / Adv Sound 1234 .const BOUNDING_BIT_DOLBY = 12; // when bit[12] = 0, all dolby ip's licenses open 1235 1236 //#define AUTH_OPTION 0x0FF2 1237 .const AUTH_BIT_DD = 0; 1238 .const AUTH_BIT_DDP = 1; 1239 .const AUTH_BIT_DDE = 2; 1240 .const AUTH_BIT_DTSDEC = 3; 1241 .const AUTH_BIT_MS10DDT = 4; 1242 .const AUTH_BIT_WMA = 5; 1243 .const AUTH_BIT_DRA = 6; 1244 .const AUTH_BIT_DTSLBR = 7; 1245 .const AUTH_BIT_GAAC = 8; 1246 .const AUTH_BIT_MS11DDT = 9; 1247 .const AUTH_BIT_DEMOMODE = 12; 1248 .const AUTH_BIT_COOK = 16; 1249 .const AUTH_BIT_DTS_HD = 17; 1250 .const AUTH_BIT_MS12_LC = 18; 1251 .const AUTH_BIT_MS12_D = 19; 1252 .const AUTH_BIT_SONICMOTION_ABS3D = 20; 1253 .const AUTH_BIT_MS12_B = 21; 1254 .const AUTH_BIT_DV258 = 22; 1255 1256 /* IP AUTH */ 1257 #define D2S_MBOX_IP_AUTH DEC2SE_MAILBOX7 1258 1259 /* PCM output port */ 1260 #define SIF_DSP_MAIN_DMX_L_OUT DEC4_PCM1_OUT 1261 #define SIF_DSP_MAIN_DMX_R_OUT DEC4_PCM2_OUT 1262 1263 !#define R2_PCM1_DMX__L_OUT DEC3_PCM1_OUT // channel mapping of PCM buffer, replace R2_DMA_READER1 (R2_DECODER1_OUTPUT_BY_DSP) 1264 !#define R2_PCM1_DMX__R_OUT DEC3_PCM2_OUT 1265 !#define R2_PCM1_MCH__L_OUT DEC3_PCM3_OUT 1266 !#define R2_PCM1_MCH__C_OUT DEC3_PCM4_OUT 1267 !#define R2_PCM1_MCH__R_OUT DEC3_PCM5_OUT 1268 !#define R2_PCM1_MCH_LS_OUT DEC3_PCM6_OUT 1269 !#define R2_PCM1_MCH_RS_OUT DEC3_PCM7_OUT 1270 !#define R2_PCM1_MCH_SW_OUT DEC3_PCM8_OUT 1271 !#define R2_PCM1_SYNTH_L DVB3_FIX_SYNTH_NF_L 1272 !#define R2_PCM1_SYNTH_H DVB3_FIX_SYNTH_NF_H 1273 1274 #define R2_PCM2_DMX__L_OUT DEC4_PCM1_OUT // channel mapping of PCM buffer, replace R2_DMA_READER2 (R2_DECODER2_OUTPUT_BY_DSP) 1275 #define R2_PCM2_DMX__R_OUT DEC4_PCM2_OUT 1276 !#define R2_PCM2_MCH__L_OUT DEC4_PCM3_OUT 1277 !#define R2_PCM2_MCH__C_OUT DEC4_PCM4_OUT 1278 !#define R2_PCM2_MCH__R_OUT DEC4_PCM5_OUT 1279 !#define R2_PCM2_MCH_LS_OUT DEC4_PCM6_OUT 1280 !#define R2_PCM2_MCH_RS_OUT DEC4_PCM7_OUT 1281 !#define R2_PCM2_MCH_SW_OUT DEC4_PCM8_OUT 1282 #define R2_PCM2_SYNTH_L DVB4_FIX_SYNTH_NF_L 1283 #define R2_PCM2_SYNTH_H DVB4_FIX_SYNTH_NF_H 1284 1285 #define DSP_SW_DMA_DMX_L_OUT DEC5_PCM1_OUT 1286 #define DSP_SW_DMA_DMX_R_OUT DEC5_PCM2_OUT 1287 #define DSP_SW_DMA_RDR_SYNTH_L DVB5_FIX_SYNTH_NF_L // SW DMA RDR use DVB5_SYNTH, MCU control, 0x112C28: Synth_L 0x112C26: Synth_H, Toggle 0x112C24[12] to update 1288 #define DSP_SW_DMA_RDR_SYNTH_H DVB5_FIX_SYNTH_NF_H 1289 1290 /************************************************ 1291 * Below is macro for DSP code only 1292 *************************************************/ 1293 #define DSP_DMA_CHECK 1294 1295 #define INC_WHILE_ONE_CNTR ar = dm (S2M_MBOX_WHILE1_CNTR); \ 1296 ay0 = 0x00FF00; \ 1297 af = ar and ay0; \ 1298 ar = ar + 0x000001; \ 1299 ay0 = 0x0000FF; \ 1300 ar = ar and ay0; \ 1301 ar = ar or af; \ 1302 dm (S2M_MBOX_WHILE1_CNTR) = ar 1303 1304 #define INC_DEBUG_CNT(x) ar = dm(kh_debugCnt+x); \ 1305 ar = ar + 1; \ 1306 dm(kh_debugCnt+x) = ar; 1307 1308 #define CONFIG_PCM_OUTPUT_PORT ar = 0; \ 1309 dm (DEC_OUT_SEL) = ar; 1310 1311 #define TRIGGER_INT_TO_MCU ar = 0x0000; IO(PDATA) = ar; \ 1312 nop; nop; nop; nop; \ 1313 nop; nop; nop; nop; \ 1314 ar = 0x8000; IO(PDATA) = ar; \ 1315 nop; nop; nop; nop; \ 1316 nop; nop; nop; nop; \ 1317 ar = 0x0000; IO(PDATA) = ar 1318 1319 /* Saft jump to i0 ~ i7 x:address, y:i0 ~ i7 */ 1320 #define I_REGISTER_JUMP(x,y) sr = lshift x by -16(lo); \ 1321 y = x; \ 1322 CPR = sr0; \ 1323 jump (y); 1324 1325 /* Saft call to i0 ~ i7 x:address, y:i0 ~ i7 */ 1326 #define I_REGISTER_CALL(x,y) sr = lshift x by -16(lo); \ 1327 y = x; \ 1328 CPR = sr0; \ 1329 call (y); 1330 1331 #define SEND_INT_TO_R2(cmd, param) ar = param; \ 1332 dm(S2D_MBOX_DSP_TO_R2_PARAM) = ar; \ 1333 ar = cmd; \ 1334 dm(S2D_MBOX_DSP_TO_R2_COMMAND) = ar 1335 1336 #else 1337 1338 #define DSP2_TO_COMMON_DRAM_OFFSET (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE) 1339 1340 /* DMA Reader Buffer */ 1341 #define DSP2_DMA_READER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_DMA_READER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1342 #define DSP2_DMA_READER_DRAM_SIZE ((DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1343 1344 /* HW DMA Reader2 Buffer */ 1345 #define DSP2_HW_DMA_READER2_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_HW_DMA_READER2_DRAM_BASE /BYTES_IN_MIU_LINE)) 1346 #define DSP2_HW_DMA_READER2_DRAM_SIZE ((HW_DMA_READER2_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1347 1348 /* Software DMA */ 1349 #define DSP2_SW_DMA_READER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_SW_DMA_READER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1350 #define DSP2_SW_DMA_READER_DRAM_SIZE ((SW_DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1351 1352 /* PCM capture buffer */ 1353 #define DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE1_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1354 #define DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE2_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1355 #define DSP2_PCM_CAPTURE3_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE3_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1356 #define DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE (PCM_CAPTURE_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE) 1357 #define DSP2_PCM_CAPTURE2_BUFFER_DRAM_SIZE (PCM_CAPTURE2_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE) 1358 #define DSP2_PCM_CAPTURE3_BUFFER_DRAM_SIZE (PCM_CAPTURE3_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE) 1359 #define DSP2_PCM_CAPTURE_COPY_WORDSIZE 32 1360 #define DSP2_PCM_CAPTURE_COPY_LINESIZE 4 1361 1362 #endif //_COMPILE_DSP_ 1363 1364 //Reseved XBox 1365 /* srs puresound */ 1366 //reserved XBox for SRS start from XBox 0xB960 1367 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED1 0xB960 1368 1369 #define SRS_PURESOUND_AeqFir_NumOfTaps_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+1 1370 #define SRS_PURESOUND_AeqIir_NumOfSections_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+2 1371 #define SRS_PURESOUND_AeqIir1Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+3 1372 #define SRS_PURESOUND_AeqIir2Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+8 1373 #define SRS_PURESOUND_AeqIir3Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+13 1374 #define SRS_PURESOUND_AeqIir4Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+18 1375 #define SRS_PURESOUND_AeqIir5Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+23 1376 #define SRS_PURESOUND_AeqIir6Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+28 1377 #define SRS_PURESOUND_AeqIir7Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+33 1378 #define SRS_PURESOUND_AeqIir8Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+38 1379 #define SRS_PURESOUND_AeqIir1_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+43 1380 #define SRS_PURESOUND_AeqIir2_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+44 1381 #define SRS_PURESOUND_AeqIir3_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+45 1382 #define SRS_PURESOUND_AeqIir4_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+46 1383 #define SRS_PURESOUND_AeqIir5_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+47 1384 #define SRS_PURESOUND_AeqIir6_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+48 1385 #define SRS_PURESOUND_AeqIir7_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+49 1386 #define SRS_PURESOUND_AeqIir8_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+50 1387 #define SRS_PURESOUND_AeqIir_Gain_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+51 1388 #define SRS_PURESOUND_AeqIir_Gain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+52 1389 #define SRS_PURESOUND_AeqFir_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+53 1390 #define SRS_PURESOUND_AeqFir_Gain_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+54 1391 #define SRS_PURESOUND_AeqFir_Gain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+55 1392 #define SRS_PURESOUND_AeqFirCoefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+64 1393 1394 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED2 SRS_PURESOUND_AeqFirCoefs_addr+1 1395 #define SRS_PURESOUND_mDummy_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2 1396 #define SRS_PURESOUND_SRS_EN_BITS_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+1 1397 #define SRS_PURESOUND_mInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+2 1398 #define SRS_PURESOUND_mOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+3 1399 #define SRS_PURESOUND_mBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+4 1400 #define SRS_PURESOUND_mHPFfc_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+5 1401 #define SRS_PURESOUND_hlInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+25 1402 #define SRS_PURESOUND_hlOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+26 1403 #define SRS_PURESOUND_hlBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+27 1404 #define SRS_PURESOUND_hlLimiterboost_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+28 1405 #define SRS_PURESOUND_hlHardLimit_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+29 1406 #define SRS_PURESOUND_hlDelaylen_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+30 1407 #define SRS_PURESOUND_AeqInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+32 1408 #define SRS_PURESOUND_AeqOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+33 1409 #define SRS_PURESOUND_AeqBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+34 1410 1411 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED_END SRS_PURESOUND_AeqBypassGain_addr 1412 1413 /* atv */ 1414 //reserved XBox for ATV 1415 #define DSP2XboxAddr_ATV_RESERVED1 DSP2XboxAddr_SRS_PURESOUND_RESERVED_END+1 1416 #define DSP2XboxAddr_AU_PAL_SYS_THRESHOLD DSP2XboxAddr_ATV_RESERVED1 1417 #define DSP2XboxAddr_SIF_PM_GAIN_TBL_PAL DSP2XboxAddr_AU_PAL_SYS_THRESHOLD+12 1418 #define DSP2XboxAddr_SIF_PM_GAIN_TBL_BTSC DSP2XboxAddr_AU_PAL_SYS_THRESHOLD+12 1419 #define DSP2XboxAddr_ATV_RESERVED_END DSP2XboxAddr_SIF_PM_GAIN_TBL_BTSC+8-1 1420 1421 /************************************************ 1422 * For Compile Pass mailbox (Need to remove later) 1423 ************************************************/ 1424 1425 #define D2M_MBOX_INTR_CMDTYPE MB_2DB2 1426 #define DSP1PmAddr_ipSecurity 0x0FF2 1427 #define D2M_MBOX_ENC_LINEADDR MB_2DAC //MPEG Encoder 1428 #define D2M_MBOX_ENC_LINESIZE MB_2DAE //MPEG Encoder 1429 #define M2D_MBOX_PIO_ID MB_2D8A 1430 #define DSP1PmAddr_smpRate 0x0FF7 1431 #define D2M_MBOX_HDMI_NPCM_LOCK MB_2DB4 //[ 3:0] Always in LSB Nibble 1432 #define MBOX_DBGCMD_RELOAD_DTV1_BEG 0xF000 1433 #define MBOX_DBGCMD_RELOAD_DTV1_END 0xF100 1434 #define MBOX_DBGCMD_RELOAD_DTV2_BEG 0xF600 1435 #define MBOX_DBGCMD_RELOAD_DTV2_END 0xF700 1436 #define DSP1DmAddr_sys_IoInfo NULL 1437 #define M2D_MBOX_MM_FILEIN_TAG MB_2D8C 1438 #define MBOX_DSP_INIT_ACK 0xE300 1439 #define D2M_MBOX_DBG_RESULT2 MB_2DBE 1440 #define D2M_MBOX_DBG_RESULT1 MB_2DBC 1441 #define M2D_MBOX_DEC_CTRL MB_2D86 1442 #define M2D_MBOX_DBG_CMD1 MB_2D9C 1443 1444 #define D2M_MBOX_DBG_RESULT1 MB_2DBC 1445 #define MBOX_DSP_INIT_ACK 0xE300 1446 #define D2M_MBOX_DBG_RESULT2 MB_2DBE 1447 #define MBOX_DSP_RELOAD_ACK1 0x0033 1448 #define MBOX_DSP_RELOAD_ACK2 0x0077 1449 #define M2D_MBOX_DEC_CTRL MB_2D86 1450 #define D2M_MBOX_SAMPLERATE MB_2DA6 1451 #define DSP1DmAddr_dec1_param 0x47A0 1452 #define DSP1DmAddr_dec1_info 0x47C0 1453 #define DSP1DmAddr_dec1_omx_param 0x42B4 1454 #define M2D_MBOX_UNI_PCM3_WRPTR MB_2D94 1455 #define DSP1PmAddr_video_TD 0x0FF1 1456 #define D2M_MBOX_UNI_PCM_BUFFEBT MB_2D6A 1457 1458 //// SIF /* SIF DSP PM vars */ // for SIF PAL DSP PM vars // 1459 #define ADDR_gain_base 0x1921 1460 #define ADDR_thr_base 0x1A20 1461 #define ADDR_pfir_base 0x1A90 // for SIF BTSC DSP PM vars // 1462 #define BTSC_COMPILE_OPTION_Addr 0x19F1 // len 1 1463 #define BTSC_OUTPUT_GAIN_Addr 0x1A21 // len 2 1464 #define BTSC_THRESHOLD_Addr 0x1A23 // len 10 1465 #define MTS_OUTPUT_GAIN_Addr 0x1A34 //len 6 1466 #define SIF_AGC_THRESHOLD_Addr 0x192D //len 3 /// PAL gain setting address 1467 #define ADDR_fm_stdM_gain ADDR_gain_base // len = 4 1468 #define ADDR_fm_stdX_gain ADDR_fm_stdM_gain+4 // len = 4 1469 #define ADDR_nicam_gain ADDR_fm_stdX_gain+4 // len = 2 1470 #define ADDR_am_gain ADDR_nicam_gain+2 // len = 2 1471 #define ADDR_agc_gain ADDR_am_gain+2 // len = 24 // PAL threshold setting address 1472 #define ADDR_a2_stdM_thr ADDR_thr_base // len = 15 1473 #define ADDR_a2_stdBG_thr ADDR_a2_stdM_thr+15 // len = 15 1474 #define ADDR_a2_stdDK_thr ADDR_a2_stdBG_thr+15 // len = 15 1475 #define ADDR_a2_stdI_thr ADDR_a2_stdDK_thr+15 // len = 4 1476 #define ADDR_am_thr ADDR_a2_stdI_thr+4 // len = 3 1477 #define ADDR_hidev_stdM_thr ADDR_am_thr+3 // len = 4 1478 #define ADDR_hidev_stdBG_thr ADDR_hidev_stdM_thr+4 // len = 4 1479 #define ADDR_hidev_stdDK_thr ADDR_hidev_stdBG_thr+4 // len = 4 1480 #define ADDR_hidev_stdI_thr ADDR_hidev_stdDK_thr+4 // len = 4 1481 #define ADDR_nicam_stdBG_pherr_thr ADDR_hidev_stdI_thr+4 //len = 3 1482 #define ADDR_nicam_stdI_pherr_thr ADDR_nicam_stdBG_pherr_thr+3 // len = 3 1483 #define ADDR_a2_bg_nicam_fm_nsr_thr 0x186F // len = 1 1484 #define ADDR_a2_dk_nicam_fm_nsr_thr 0x1870 // len = 1 // pfir setting address 1485 #define ADDR_hidev_demfir ADDR_pfir_base // len = 15 1486 #define ADDR_fm_ch1_pfir ADDR_hidev_demfir+16 // len = 30 1487 #define ADDR_fm_ch2_pfir ADDR_fm_ch1_pfir+30 // len = 30 1488 #define ADDR_hidev_lv1_pfir ADDR_fm_ch2_pfir+30 // len = 20 1489 #define ADDR_hidev_lv2_pfir ADDR_hidev_lv1_pfir+20 // len = 20 1490 #define ADDR_hidev_lv3_pfir ADDR_hidev_lv2_pfir+20 // len = 20 // BTSC threshold setting address 1491 #define HIDEV_NSR_THRESHOLD_Addr BTSC_THRESHOLD_Addr+10 // len 2 1492 #define BTSC_MONO_AMP_THRESHOLD_Addr HIDEV_NSR_THRESHOLD_Addr+2 // len 2 1493 #define HIDEV_AMP_THRESHOLD_Addr BTSC_MONO_AMP_THRESHOLD_Addr+2 // len 2 1494 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr HIDEV_AMP_THRESHOLD_Addr+2 // len 1 1495 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr MTS_OUTPUT_GAIN_Addr+6 // len 3 1496 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr+3 // len 1 1497 1498 #define M2S_MBOX_MM_FILEIN_TAG MB_2DCC //[7:0] 1499 #define DSP2PmAddr_smpRate 0x0D49 1500 #define DSP2PmAddr_soundMode 0x0D4A 1501 #define DSP2DmAddr_dec1_param 0x4390 1502 #define DSP2DmAddr_hdmi_debugInfo 0x396A 1503 #define DSP2DmAddr_spdif_debugInfo 0x3832 1504 1505 /* SIF DSP PM vars */ 1506 /* for SIF PAL DSP PM vars */ 1507 1508 #define ADDR_gain_base_2 NULL 1509 #define ADDR_thr_base_2 NULL 1510 #define ADDR_pfir_base_2 NULL 1511 // for SIF BTSC DSP PM vars // 1512 #define BTSC_COMPILE_OPTION_Addr_2 NULL // len 1 1513 #define BTSC_OUTPUT_GAIN_Addr_2 NULL // len 2 1514 #define BTSC_THRESHOLD_Addr_2 NULL // len 10 1515 #define MTS_OUTPUT_GAIN_Addr_2 NULL //len 6 1516 #define SIF_AGC_THRESHOLD_Addr_2 NULL //len 3 1517 1518 /// PAL gain setting address 1519 #define ADDR_fm_stdM_gain_2 NULL // len = 4 1520 #define ADDR_fm_stdX_gain_2 NULL // len = 4 1521 #define ADDR_nicam_gain_2 NULL // len = 2 1522 #define ADDR_am_gain_2 NULL // len = 2 1523 #define ADDR_agc_gain_2 NULL // len = 24 1524 1525 // PAL threshold setting address 1526 #define ADDR_a2_stdM_thr_2 NULL // len = 15 1527 #define ADDR_a2_stdBG_thr_2 NULL // len = 15 1528 #define ADDR_a2_stdDK_thr_2 NULL // len = 15 1529 #define ADDR_a2_stdI_thr_2 NULL // len = 4 1530 #define ADDR_am_thr_2 NULL // len = 3 1531 #define ADDR_hidev_stdM_thr_2 NULL // len = 4 1532 #define ADDR_hidev_stdBG_thr_2 NULL // len = 4 1533 #define ADDR_hidev_stdDK_thr_2 NULL // len = 4 1534 #define ADDR_hidev_stdI_thr_2 NULL // len = 4 1535 #define ADDR_nicam_stdBG_pherr_thr_2 NULL //len = 3 1536 #define ADDR_nicam_stdI_pherr_thr_2 NULL // len = 3 1537 #define ADDR_a2_bg_nicam_fm_nsr_thr_2 NULL // len = 1 1538 #define ADDR_a2_dk_nicam_fm_nsr_thr_2 NULL // len = 1 1539 1540 // pfir setting address 1541 #define ADDR_hidev_demfir_2 NULL // len = 15 1542 #define ADDR_fm_ch1_pfir_2 NULL // len = 30 1543 #define ADDR_fm_ch2_pfir_2 NULL // len = 30 1544 #define ADDR_hidev_lv1_pfir_2 NULL // len = 20 1545 #define ADDR_hidev_lv2_pfir_2 NULL // len = 20 1546 #define ADDR_hidev_lv3_pfir_2 NULL // len = 20 1547 1548 // BTSC threshold setting address 1549 #define HIDEV_NSR_THRESHOLD_Addr_2 NULL // len 2 1550 #define BTSC_MONO_AMP_THRESHOLD_Addr_2 NULL // len 2 1551 #define HIDEV_AMP_THRESHOLD_Addr_2 NULL // len 2 1552 1553 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr_2 NULL // len 1 1554 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2 NULL // len 3 1555 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr_2 NULL // len 1 1556 1557 /************************************************ 1558 * End for Compile Pass mailbox (Need to remove later) 1559 ************************************************/ 1560 1561 1562 #endif //_AUDIO_COMM2_H_ 1563 1564