Searched refs:MULTI_CH_INPUT_DLY_DRAM_SIZE (Results 1 – 18 of 18) sorted by relevance
139 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…686 #if(MULTI_CH_INPUT_DLY_DRAM_SIZE>0)688 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE…
89 …#define MULTI_CH_INPUT_DLY_DRAM_SIZE 0x00000 // 6ch (256 ms), can be adjusted by re… macro
146 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…711 #if(MULTI_CH_INPUT_DLY_DRAM_SIZE>0)713 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) …
147 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…750 #if(MULTI_CH_INPUT_DLY_DRAM_SIZE>0)752 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) …
77 …#define MULTI_CH_INPUT_DLY_DRAM_SIZE 0x00000 // 6ch (256 ms), can be adjusted by r… macro
153 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…905 #if(MULTI_CH_INPUT_DLY_DRAM_SIZE>0)907 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) …
51 …#define MULTI_CH_INPUT_DLY_DRAM_SIZE 0x00000 // 6ch (128 ms), can be adjusted by re… macro
146 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…841 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE…
51 …#define MULTI_CH_INPUT_DLY_DRAM_SIZE 0x1B000 // 6ch (128 ms), can be adjusted by re… macro
146 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…875 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE…
146 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…857 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE…
95 …#define MULTI_CH_INPUT_DLY_DRAM_SIZE 0x6C000 // 6ch (512 ms), can be adjusted by re… macro
146 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…863 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE…
146 …#define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_ST…866 ….const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE…