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Searched refs:MIU2_REG_HVD_BASE2 (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h401 #define MIU2_REG_HVD_BASE2 (0x62300) macro
421 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
422 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h409 #define MIU2_REG_HVD_BASE2 (0x62300) macro
429 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
430 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h409 #define MIU2_REG_HVD_BASE2 (0x62300) macro
429 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
430 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h409 #define MIU2_REG_HVD_BASE2 (0x62300) macro
429 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
430 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h429 #define MIU2_REG_HVD_BASE2 (0x62300) macro
449 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
450 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h429 #define MIU2_REG_HVD_BASE2 (0x62300) macro
449 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
450 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h427 #define MIU2_REG_HVD_BASE2 (0x62300) macro
447 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
448 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h599 #define MIU2_REG_HVD_BASE2 (0x62300) macro
636 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
637 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h600 #define MIU2_REG_HVD_BASE2 (0x62300) macro
637 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
638 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h600 #define MIU2_REG_HVD_BASE2 (0x62300) macro
637 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
638 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h601 #define MIU2_REG_HVD_BASE2 (0x62300) macro
638 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
639 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h599 #define MIU2_REG_HVD_BASE2 (0x62300) macro
636 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
637 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h600 #define MIU2_REG_HVD_BASE2 (0x62300) macro
637 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
638 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h645 #define MIU2_REG_HVD_BASE2 (0x62300) macro
680 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
681 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h628 #define MIU2_REG_HVD_BASE2 (0x62300) macro
664 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1))
665 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1))