Home
last modified time | relevance | path

Searched refs:MIU2_REG_HVD_BASE (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h400 #define MIU2_REG_HVD_BASE (0x62000) macro
417 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
418 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
419 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
420 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
432 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
433 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
434 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
435 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
436 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h408 #define MIU2_REG_HVD_BASE (0x62000) macro
425 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
426 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
427 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
428 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
440 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
441 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
442 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
443 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
444 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h408 #define MIU2_REG_HVD_BASE (0x62000) macro
425 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
426 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
427 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
428 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
440 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
441 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
442 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
443 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
444 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h408 #define MIU2_REG_HVD_BASE (0x62000) macro
425 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
426 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
427 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
428 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
440 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
441 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
442 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
443 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
444 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h428 #define MIU2_REG_HVD_BASE (0x62000) macro
445 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
446 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
447 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
448 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
460 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
461 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
462 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
463 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
464 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h428 #define MIU2_REG_HVD_BASE (0x62000) macro
445 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
446 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
447 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
448 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
460 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
461 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
462 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
463 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
464 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h426 #define MIU2_REG_HVD_BASE (0x62000) macro
443 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
444 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
445 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
446 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
458 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
459 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
460 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
461 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
462 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h598 #define MIU2_REG_HVD_BASE (0x62000) macro
607 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
632 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
633 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
634 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
635 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
649 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
650 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
651 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
652 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h599 #define MIU2_REG_HVD_BASE (0x62000) macro
608 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
633 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
634 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
635 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
636 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
650 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
651 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
652 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
653 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h599 #define MIU2_REG_HVD_BASE (0x62000) macro
608 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
633 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
634 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
635 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
636 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
650 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
651 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
652 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
653 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h600 #define MIU2_REG_HVD_BASE (0x62000) macro
609 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
634 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
635 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
636 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
637 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
651 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
652 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
653 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
654 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h598 #define MIU2_REG_HVD_BASE (0x62000) macro
607 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
632 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
633 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
634 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
635 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
649 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
650 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
651 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
652 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h599 #define MIU2_REG_HVD_BASE (0x62000) macro
608 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
633 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
634 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
635 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
636 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
650 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
651 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
652 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
653 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h644 #define MIU2_REG_HVD_BASE (0x62000) macro
652 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
676 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
677 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
678 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
679 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
693 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
694 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
695 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
696 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h627 #define MIU2_REG_HVD_BASE (0x62000) macro
636 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1))
660 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1))
661 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1))
662 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1))
663 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1))
675 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1))
676 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1))
677 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1))
678 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1))
[all …]