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Searched refs:MIU1_REG_HVD_BASE (Results 1 – 25 of 62) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DregHVD.h427 #define MIU1_REG_HVD_BASE (0x0600) macro
433 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
434 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
435 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
436 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DregHVD.h427 #define MIU1_REG_HVD_BASE (0x0600) macro
433 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
434 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
435 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
436 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DregHVD.h427 #define MIU1_REG_HVD_BASE (0x0600) macro
433 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
434 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
435 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
436 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DregHVD.h427 #define MIU1_REG_HVD_BASE (0x0600) macro
433 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
434 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
435 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
436 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DregHVD.h427 #define MIU1_REG_HVD_BASE (0x0600) macro
433 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
434 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
435 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
436 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DregHVD.h427 #define MIU1_REG_HVD_BASE (0x0600) macro
433 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
434 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
435 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
436 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/hvd_ex/
H A DregHVD_EX.h526 #define MIU1_REG_HVD_BASE (0x0600) macro
532 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
533 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
534 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
535 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
541 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/hvd_ex/
H A DregHVD_EX.h526 #define MIU1_REG_HVD_BASE (0x0600) macro
532 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
533 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
534 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
535 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
541 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/hvd_v3/
H A DregHVD_EX.h530 #define MIU1_REG_HVD_BASE (0x0600) macro
536 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
537 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
538 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
539 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
545 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DregHVD_EX.h548 #define MIU1_REG_HVD_BASE (0x0600) macro
554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DregVPU.h348 #define MIU1_REG_HVD_BASE (0x0600) macro
354 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
355 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
356 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
357 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DregVPU_EX.h355 #define MIU1_REG_HVD_BASE (0x0600UL) macro
361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
362 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
363 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
364 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DregVPU.h348 #define MIU1_REG_HVD_BASE (0x0600) macro
354 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
355 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
356 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
357 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DregVPU_EX.h355 #define MIU1_REG_HVD_BASE (0x0600UL) macro
361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
362 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
363 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
364 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DregVPU_EX.h355 #define MIU1_REG_HVD_BASE (0x0600UL) macro
361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
362 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
363 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
364 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DregVPU_EX.h355 #define MIU1_REG_HVD_BASE (0x0600UL) macro
361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
362 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
363 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
364 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DregVPU.h348 #define MIU1_REG_HVD_BASE (0x0600) macro
354 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
355 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
356 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
357 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DregVPU_EX.h355 #define MIU1_REG_HVD_BASE (0x0600UL) macro
361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1))
362 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1))
363 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1))
364 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1))

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