Home
last modified time | relevance | path

Searched refs:INTERNAL_DVBT2_DRAM_OFFSET (Results 1 – 3 of 3) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT2.c133 #define INTERNAL_DVBT2_DRAM_OFFSET 0x5000 macro
134 #define INTERNAL_DVBT2_FW_LEN (0x10000 - INTERNAL_DVBT2_DRAM_OFFSET)
1130 HAL_DMD_RIU_WriteByte(0x111707,(INTERNAL_DVBT2_DRAM_OFFSET-1)>>8); in INTERN_DVBT2_InitClkgen()
1131 HAL_DMD_RIU_WriteByte(0x111706,(INTERNAL_DVBT2_DRAM_OFFSET-1)&0xff); in INTERN_DVBT2_InitClkgen()
1142 HAL_DMD_RIU_WriteByte(0x11170d,INTERNAL_DVBT2_DRAM_OFFSET>>8); in INTERN_DVBT2_InitClkgen()
1143 HAL_DMD_RIU_WriteByte(0x11170c,INTERNAL_DVBT2_DRAM_OFFSET&0xff); in INTERN_DVBT2_InitClkgen()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT2.c133 #define INTERNAL_DVBT2_DRAM_OFFSET 0x5000 macro
134 #define INTERNAL_DVBT2_FW_LEN (0x10000 - INTERNAL_DVBT2_DRAM_OFFSET)
1143 HAL_DMD_RIU_WriteByte(0x111707,(INTERNAL_DVBT2_DRAM_OFFSET-1)>>8); in INTERN_DVBT2_InitClkgen()
1144 HAL_DMD_RIU_WriteByte(0x111706,(INTERNAL_DVBT2_DRAM_OFFSET-1)&0xff); in INTERN_DVBT2_InitClkgen()
1155 HAL_DMD_RIU_WriteByte(0x11170d,INTERNAL_DVBT2_DRAM_OFFSET>>8); in INTERN_DVBT2_InitClkgen()
1156 HAL_DMD_RIU_WriteByte(0x11170c,INTERNAL_DVBT2_DRAM_OFFSET&0xff); in INTERN_DVBT2_InitClkgen()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT2.c133 #define INTERNAL_DVBT2_DRAM_OFFSET 0x5000 macro
134 #define INTERNAL_DVBT2_FW_LEN (0x10000 - INTERNAL_DVBT2_DRAM_OFFSET)
1143 HAL_DMD_RIU_WriteByte(0x111707,(INTERNAL_DVBT2_DRAM_OFFSET-1)>>8); in INTERN_DVBT2_InitClkgen()
1144 HAL_DMD_RIU_WriteByte(0x111706,(INTERNAL_DVBT2_DRAM_OFFSET-1)&0xff); in INTERN_DVBT2_InitClkgen()
1155 HAL_DMD_RIU_WriteByte(0x11170d,INTERNAL_DVBT2_DRAM_OFFSET>>8); in INTERN_DVBT2_InitClkgen()
1156 HAL_DMD_RIU_WriteByte(0x11170c,INTERNAL_DVBT2_DRAM_OFFSET&0xff); in INTERN_DVBT2_InitClkgen()