Searched refs:CKG_VBY1_VMODE_LPLL_FIFO_DIV4 (Results 1 – 2 of 2) sorted by relevance
252 #define CKG_VBY1_VMODE_LPLL_FIFO_DIV4 (0x0A) macro
2491 … u16_fifo_odclk_data = (CKG_VBY1_VMODE_LPLL_FIFO_DIV4 | CKG_ODCLK_A_GATED | CKG_NOSSC_ODCLK_GATED); in MHal_PNL_Init_XC_Clk()