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Searched refs:CKG_S2_FCLK_320MHZ (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h820 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
822 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h802 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
804 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h866 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
868 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h981 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
983 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h936 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
938 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h993 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
995 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h930 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
932 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h998 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
1000 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h985 #define CKG_S2_FCLK_320MHZ (6 << 2) macro
987 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c3431 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c3636 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_sc.c3916 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c4266 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c4286 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c4574 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c4574 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK); in Hal_SC_set_Fclk()