| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_dip.c | 1229 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_Init()
1300 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1470 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1570 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
3315 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_dip.c | 1230 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_Init()
1301 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1471 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1571 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
3317 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_dip.c | 1568 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1855 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
4268 …MDrv_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable clock in HAL_XC_DIP_InterruptDetach()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 904 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 910 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 903 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 897 #define CKG_PDW1_GATED BIT(0) macro
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| H A D | mhal_xc_chip_config.h.0 | 896 #define CKG_PDW1_GATED BIT(0)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 773 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 880 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 841 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 892 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 827 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 897 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 884 #define CKG_PDW1_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_dip.c | 687 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_dip.c | 839 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_dip.c | 798 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_dip.c | 800 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_dip.c | 720 MDrv_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_dip.c | 1230 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_dip.c | 1230 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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