| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_dip.c | 1188 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_Init()
1292 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1457 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1562 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
3307 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_dip.c | 1189 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_Init()
1293 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1458 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1563 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
3309 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_dip.c | 1471 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disab… in HAL_XC_DIP_Init()
1559 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1754 …MDrv_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable clock in HAL_XC_DIP_ClearIntr()
1846 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
4258 …MDrv_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable clock in HAL_XC_DIP_InterruptDetach()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | mhal_xc_chip_config.h | 605 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | mhal_xc_chip_config.h | 605 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 892 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 898 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 891 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 885 #define CKG_PDW0_GATED BIT(0) macro
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| H A D | mhal_xc_chip_config.h.0 | 884 #define CKG_PDW0_GATED BIT(0)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 759 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 866 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 827 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 878 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 813 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 883 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 870 #define CKG_PDW0_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_dip.c | 484 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_dip.c | 503 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_dip.c | 657 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_dip.c | 809 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_dip.c | 767 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_dip.c | 769 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_dip.c | 690 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_dip.c | 1189 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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