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Searched refs:CKG_IDCLK1_MASK (Results 1 – 25 of 71) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_ip.c203 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
204 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
213 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
H A Dmhal_dip.c1051 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
1109 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_ip.c203 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
204 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
213 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
H A Dmhal_dip.c1034 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
1096 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_ip.c221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
H A Dmhal_offline.c399 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // initial to … in Hal_XC_SetOfflineDetectClk()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c248 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
249 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
258 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
259 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_ip.c221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_ip.c221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
H A Dmhal_offline.c394 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // initial to … in Hal_XC_SetOfflineDetectClk()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_ip.c221 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
222 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
231 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
232 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c223 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
233 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
234 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c214 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
215 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
224 …MDrv_WriteByteMask(REG_CKG_IDCLK1, CKG_IDCLK1_XTAL, CKG_IDCLK1_MASK); // Sub window reset to XTAL … in Hal_SC_ip_software_reset()
225 …MDrv_WriteByteMask(REG_CKG_IDCLK1, u8CLK1Mux, CKG_IDCLK1_MASK); // Sub window reset to XTAL when A… in Hal_SC_ip_software_reset()
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h435 #define CKG_IDCLK1_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h435 #define CKG_IDCLK1_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h435 #define CKG_IDCLK1_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h435 #define CKG_IDCLK1_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h435 #define CKG_IDCLK1_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h435 #define CKG_IDCLK1_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro

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