Home
last modified time | relevance | path

Searched refs:CHIP_REG_BASE (Results 1 – 25 of 129) sorted by relevance

123456

/utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
412 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
426 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE)
430 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0xAF)
444 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel
445 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x0B) //reg_stc1_cw_sel
446 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
447 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
448 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x10)
449 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x12)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
386 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
396 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
406 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
411 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x08) //reg_stc0_cw_sel
412 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x09) //reg_stc1_cw_sel
413 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
414 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
415 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
416 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
402 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
412 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
422 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
427 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x08) //reg_stc0_cw_sel
428 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x09) //reg_stc1_cw_sel
429 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
430 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
431 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
432 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
387 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
397 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
407 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
412 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x08) //reg_stc0_cw_sel
413 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x09) //reg_stc1_cw_sel
414 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
415 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
416 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
417 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
399 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
409 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
419 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
424 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x08) //reg_stc0_cw_sel
425 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x09) //reg_stc1_cw_sel
426 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
427 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
428 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
429 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
434 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
448 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE)
452 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0xAF)
466 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel
467 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x0B) //reg_stc1_cw_sel
468 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
469 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
470 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x10)
471 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x12)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
399 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
409 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
419 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
424 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x08) //reg_stc0_cw_sel
425 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x09) //reg_stc1_cw_sel
426 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
427 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
428 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
429 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
383 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
393 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
403 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
408 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x08) //reg_stc0_cw_sel
409 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x09) //reg_stc1_cw_sel
410 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
411 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
412 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
413 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
409 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
423 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0xAF)
436 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
441 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel
442 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x0B) //reg_stc1_cw_sel
443 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
444 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
445 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x10)
446 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x12)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
406 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
420 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0xAF)
433 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
438 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel
439 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x0B) //reg_stc1_cw_sel
440 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
441 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
442 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x10)
443 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x12)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
407 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
421 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0xAF)
434 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
439 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel
440 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x0B) //reg_stc1_cw_sel
441 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
442 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
443 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x10)
444 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x12)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/M5621/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
395 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
404 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
413 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
418 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel
419 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
420 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
421 #define REG_STC1_CW_L (CHIP_REG_BASE + 0xE2)
422 #define REG_STC1_CW_H (CHIP_REG_BASE + 0xE4)
423 #define REG_TSP_CLK (CHIP_REG_BASE + 0x54) //reg_ckg_tsp
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
475 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
489 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE)
493 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0xAF)
507 #define REG_STC_CW_SLE_L (CHIP_REG_BASE + 0x0A) //reg_stc0_cw_sel
508 #define REG_STC_CW_SLE_H (CHIP_REG_BASE + 0x0B) //reg_stc1_cw_sel
509 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
510 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
511 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x10)
512 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x12)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/mustang/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
366 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
375 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
384 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
389 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0C)
390 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0E)
391 #define REG_STC1_CW_L (CHIP_REG_BASE + 0xE2)
392 #define REG_STC1_CW_H (CHIP_REG_BASE + 0xE4)
395 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0x0A)
400 #define REG_DC0_NUM (CHIP_REG_BASE + 0x14)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/messi/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
384 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
394 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
404 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
409 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
410 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
411 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
412 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
415 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0xE0)
418 #define REG_DC0_FREERUN_CW_L (CHIP_REG_BASE + 0xE4)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
377 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
387 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
397 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
402 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
403 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
404 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
405 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
408 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0xE0)
411 #define REG_DC0_FREERUN_CW_L (CHIP_REG_BASE + 0xE4)
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/mainz/mvop/
H A DregMVOP.h114 #define CHIP_REG_BASE 0x0B00 //chiptop CLKGEN0 macro
384 #define REG_CKG_DC0 (CHIP_REG_BASE + 0x98)
394 #define REG_CKG_SUB_DC0 (CHIP_REG_BASE + 0x9A)
404 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E)
409 #define REG_STC0_CW_L (CHIP_REG_BASE + 0x0A)
410 #define REG_STC0_CW_H (CHIP_REG_BASE + 0x0C)
411 #define REG_STC1_CW_L (CHIP_REG_BASE + 0x0E)
412 #define REG_STC1_CW_H (CHIP_REG_BASE + 0x10)
415 #define REG_UPDATE_DC0_CW (CHIP_REG_BASE + 0xE0)
418 #define REG_DC0_FREERUN_CW_L (CHIP_REG_BASE + 0xE4)
[all …]
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6F*2)+1) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6F*2)+1) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6F*2)+1) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h110 #define CHIP_REG_BASE (0x1E00) macro
113 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
119 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
125 #define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC
131 #define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE
136 #define CHIP_REG_HWI2C_MIIC3 (CHIP_REG_BASE+ (0x6F*2)+1) //0x1EDC
142 #define CHIP_REG_HWI2C_MIIC4 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
148 #define CHIP_REG_HWI2C_MIIC5 (CHIP_REG_BASE+ (0x6F*2)) //0x1EDC
154 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1)

123456