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/utopia/UTPA2-700.0.x/modules/gpio/hal/maldives/gpio/
H A DhalGPIO.c111 #define BIT6 BIT(6) macro
269 #define GPIO28_OUT 0x0e4e, BIT6
284 #define GPIO31_OUT 0x0496, BIT6
294 #define GPIO33_OUT 0x0497, BIT6
304 #define GPIO35_OUT 0x0498, BIT6
314 #define GPIO37_OUT 0x0499, BIT6
354 #define GPIO45_OUT 0x0494, BIT6
388 #define GPIO52_OEN 0x101e5C, BIT6
389 #define GPIO52_OUT 0x101e56, BIT6
390 #define GPIO52_IN 0x101e50, BIT6
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/utopia/UTPA2-700.0.x/modules/gpio/hal/mustang/gpio/
H A DhalGPIO.c111 #define BIT6 BIT(6) macro
269 #define GPIO28_OUT 0x0e4e, BIT6
284 #define GPIO31_OUT 0x0496, BIT6
294 #define GPIO33_OUT 0x0497, BIT6
304 #define GPIO35_OUT 0x0498, BIT6
314 #define GPIO37_OUT 0x0499, BIT6
354 #define GPIO45_OUT 0x0494, BIT6
403 #define GPIO55_OEN 0x101e5C, BIT6
404 #define GPIO55_OUT 0x101e56, BIT6
405 #define GPIO55_IN 0x101e50, BIT6
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/utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/
H A DregMVOP.h145 #define VOP_EXTFLD_EN BIT6
152 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
181 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
218 #define VOP_R2_WISHBONE BIT6
227 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
247 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
255 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
268 #define VOP_MIU_REQ_DIS BIT6
279 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
296 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
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/utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/
H A DregMVOP.h144 #define VOP_EXTFLD_EN BIT6
151 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
180 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
213 #define VOP_R2_WISHBONE BIT6
222 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
242 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
250 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
263 #define VOP_MIU_REQ_DIS BIT6
274 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
291 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
[all …]
/utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/
H A DregMVOP.h144 #define VOP_EXTFLD_EN BIT6
151 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
179 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
210 #define VOP_R2_WISHBONE BIT6
219 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
239 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
247 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
260 #define VOP_MIU_REQ_DIS BIT6
271 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
288 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
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/utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/
H A DregMVOP.h142 #define VOP_EXTFLD_EN BIT6
149 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
177 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
207 #define VOP_R2_WISHBONE BIT6
216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
236 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
244 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
257 #define VOP_MIU_REQ_DIS BIT6
268 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
285 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
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/utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/
H A DregMVOP.h142 #define VOP_EXTFLD_EN BIT6
149 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
178 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
208 #define VOP_R2_WISHBONE BIT6
217 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
237 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
245 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
258 #define VOP_MIU_REQ_DIS BIT6
269 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
286 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
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/utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/
H A DregMVOP.h144 #define VOP_EXTFLD_EN BIT6
151 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
180 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
213 #define VOP_R2_WISHBONE BIT6
222 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
242 #define VOP_DMA_STATUS (BIT7 | BIT6 | BIT5 | BIT4)
250 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
263 #define VOP_MIU_REQ_DIS BIT6
274 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
291 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
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/utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
177 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
212 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
214 #define VOP_R2_WISHBONE BIT6
241 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
254 #define VOP_MIU_REQ_DIS BIT6
262 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
279 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
287 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
301 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/messi/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
177 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
208 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
210 #define VOP_R2_WISHBONE BIT6
237 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
250 #define VOP_MIU_REQ_DIS BIT6
258 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
275 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
283 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
297 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
177 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
208 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
210 #define VOP_R2_WISHBONE BIT6
237 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
250 #define VOP_MIU_REQ_DIS BIT6
258 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
275 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
283 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
297 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
177 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
214 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
217 #define VOP_R2_WISHBONE BIT6
244 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
257 #define VOP_MIU_REQ_DIS BIT6
265 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
282 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
290 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
304 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/mainz/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
177 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
208 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
210 #define VOP_R2_WISHBONE BIT6
237 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
250 #define VOP_MIU_REQ_DIS BIT6
258 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
275 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
283 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
297 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/
H A DregMVOP.h152 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
179 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
218 #define VOP_R2_WISHBONE BIT6
245 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
258 #define VOP_MIU_REQ_DIS BIT6
266 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
283 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
291 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
305 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/
H A DregMVOP.h150 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
178 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
215 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
218 #define VOP_R2_WISHBONE BIT6
245 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
258 #define VOP_MIU_REQ_DIS BIT6
266 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
283 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
291 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
305 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
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/utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/
H A DregMVOP.h152 #define VOP_MVD_VS_MD BIT6 //u3 new 0: Original mode;1: Use new vsync (tf_vs_mvd, bf_vs_mvd)
179 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
216 #define VOP_DEBUG_SEL (BIT5 | BIT6 | BIT7) //u3 new: MVOP debug out select
219 #define VOP_R2_WISHBONE BIT6
246 #define VOP_RIU_DEBUG_SEL (BIT6|BIT7) //RIU debug register select
259 #define VOP_MIU_REQ_DIS BIT6
267 #define VOP_MSB_BUF1_MIU_SEL (BIT6|BIT7) // UV miu select: miu0~3 = 0x0~0x3
284 #define VOP_INFO_FROM_CODEC_COMP_MODE (BIT6) //compression mode
292 #define VOP_INFO_FROM_CODEC_10BIT (BIT6) //10 bits enable
306 #define VOP_LSB_BUF1_MIU_SEL (BIT6|BIT7) // LSB UV miu select: miu0~3 = 0x0~0x3
[all …]
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
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/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
[all …]
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
[all …]
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
[all …]
/utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
[all …]
/utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/
H A DregCLKGEN.h113 #define CKG_MIU_MASK (BIT7 | BIT6)
137 #define CKG_AEON_GATED BIT6
152 #define CKG_STC0_MASK (BIT7 | BIT6)
161 #define CKG_MAD_STC_MASK (BIT7 | BIT6)
179 #define CKG_MVD_MASK (BIT7 | BIT6)
196 #define CKG_DC0_MASK (BIT7 | BIT6)
220 #define CKG_GE_MASK (BIT7 | BIT6)
238 #define CKG_GOPG1_MASK (BIT7 | BIT6)
256 #define CKG_VD_MASK (BIT7 | BIT6)
274 #define CKG_VD200_MASK (BIT7 | BIT6)
[all …]

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