| /rockchip-linux_mpp/mpp/hal/vpu/jpege/ |
| H A D | hal_jpege_vepu1_v2.c | 179 RK_U32 width_align = MPP_ALIGN(width, 16); in hal_jpege_vepu1_gen_regs() local
210 MPP_SWAP(RK_U32, width_align, ver_stride); in hal_jpege_vepu1_gen_regs()
223 x_fill = (width_align - width) / 4; in hal_jpege_vepu1_gen_regs()
282 ((width_align >> 4) << 19) | in hal_jpege_vepu1_gen_regs()
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| H A D | hal_jpege_vepu2_v2.c | 373 RK_U32 width_align = MPP_ALIGN(width, 16); in hal_jpege_vepu2_gen_regs() local
405 MPP_SWAP(RK_U32, width_align, ver_stride); in hal_jpege_vepu2_gen_regs()
417 x_fill = (width_align - width) / 4; in hal_jpege_vepu2_gen_regs()
525 regs[103] = (width_align >> 4) << 8 | in hal_jpege_vepu2_gen_regs()
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| /rockchip-linux_mpp/mpp/hal/vpu/vp8e/ |
| H A D | hal_vp8e_base.c | 992 RK_S32 width_align = MPP_ALIGN(set->width, 16); in set_parameter() local
1010 MPP_SWAP(RK_S32, width_align, height_align); in set_parameter()
1016 ctx->mb_per_frame = width_align / 16 * height_align / 16; in set_parameter()
1017 ctx->mb_per_row = width_align / 16; in set_parameter()
1020 sps->pic_width_in_pixel = width_align; in set_parameter()
1022 sps->pic_width_in_mbs = width_align / 16; in set_parameter()
1105 hw_cfg->mbs_in_row = width_align / 16; in set_parameter()
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| /rockchip-linux_mpp/mpp/hal/rkenc/h264e/ |
| H A D | hal_h264e_vepu511.c | 821 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16); in vepu511_h264e_save_pass1_patch() local
825 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu511_h264e_save_pass1_patch()
837 mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align); in vepu511_h264e_save_pass1_patch()
850 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16); in vepu511_h264e_use_pass1_patch() local
852 RK_S32 y_stride = width_align; in vepu511_h264e_use_pass1_patch()
874 mpp_dev_multi_offset_update(ctx->offsets, 161, width_align * height_align); in vepu511_h264e_use_pass1_patch()
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| H A D | hal_h264e_vepu580.c | 828 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 64); in vepu580_h264e_save_pass1_patch() local
832 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu580_h264e_save_pass1_patch()
844 mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align); in vepu580_h264e_save_pass1_patch()
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| H A D | hal_h264e_vepu510.c | 849 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16); in vepu510_h264e_save_pass1_patch() local
853 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu510_h264e_save_pass1_patch()
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| /rockchip-linux_mpp/mpp/hal/rkenc/h265e/ |
| H A D | hal_h265e_vepu511.c | 666 RK_S32 width_align = MPP_ALIGN(width, 16); in vepu511_h265e_save_pass1_patch() local
670 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu511_h265e_save_pass1_patch()
685 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height_align); in vepu511_h265e_save_pass1_patch()
698 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16); in vepu511_h265e_use_pass1_patch() local
700 RK_S32 y_stride = width_align; in vepu511_h265e_use_pass1_patch()
723 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, width_align * height_align); in vepu511_h265e_use_pass1_patch()
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| H A D | hal_h265e_vepu580.c | 2543 RK_S32 width_align = MPP_ALIGN(width, 64); in vepu580_h265e_save_pass1_patch() local
2547 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu580_h265e_save_pass1_patch()
2562 mpp_dev_multi_offset_update(frm->reg_cfg, 164, width_align * height_align); in vepu580_h265e_save_pass1_patch()
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| H A D | hal_h265e_vepu510.c | 1689 RK_S32 width_align = MPP_ALIGN(width, 16); in vepu510_h265e_save_pass1_patch() local
1693 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu510_h265e_save_pass1_patch()
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