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Searched refs:reg_frm (Results 1 – 10 of 10) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu510.c701 H264eVepu510Frame *reg_frm = &regs->reg_frm; in setup_vepu510_prep() local
715 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu510_prep()
716 reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu510_prep()
717 reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu510_prep()
718 reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu510_prep()
722 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu510_prep()
723 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu510_prep()
724 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu510_prep()
725 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu510_prep()
789 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu510_prep()
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H A Dhal_h264e_vepu511.c700 H264eVepu511Frame *reg_frm = &regs->reg_frm; in setup_vepu511_prep() local
714 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu511_prep()
715 reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu511_prep()
716 reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu511_prep()
717 reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu511_prep()
721 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu511_prep()
722 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu511_prep()
723 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu511_prep()
724 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu511_prep()
727 reg_frm->common.src_proc.rkfbcd_en = 1; in setup_vepu511_prep()
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H A Dhal_h264e_vepu510_tune.c59 H264eVepu510Frame *reg_frm = &regs->reg_frm; in vepu510_h264e_tune_qpmap_init() local
83 reg_frm->common.adr_roir = roir_buf_fd; in vepu510_h264e_tune_qpmap_init()
H A Dhal_h264e_vepu510_reg.h632 H264eVepu510Frame reg_frm; member
H A Dhal_h264e_vepu511_reg.h1194 H264eVepu511Frame reg_frm; member
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu510.c1301 H265eVepu510Frame *reg_frm = &regs->reg_frm; in vepu510_h265_set_rc_regs() local
1315 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1316 reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1317 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1318 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1327 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1328 reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1329 reg_frm->common.rc_cfg.rc_en = 1; in vepu510_h265_set_rc_regs()
1330 reg_frm->common.rc_cfg.aq_en = 1; in vepu510_h265_set_rc_regs()
1331 reg_frm->common.rc_cfg.rc_ctu_num = mb_wd32; in vepu510_h265_set_rc_regs()
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H A Dhal_h265e_vepu511.c663 H265eVepu511Frame *reg_frm = &regs->reg_frm; in vepu511_h265e_save_pass1_patch() local
677 reg_frm->common.enc_pic.cur_frm_ref = 1; in vepu511_h265e_save_pass1_patch()
678 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); in vepu511_h265e_save_pass1_patch()
679 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr; in vepu511_h265e_save_pass1_patch()
680 reg_frm->common.enc_pic.rec_fbc_dis = 1; in vepu511_h265e_save_pass1_patch()
683 reg_frm->synt_pps.lpf_fltr_acrs_til = 0; in vepu511_h265e_save_pass1_patch()
688 reg_frm->common.sli_splt.sli_splt = 0; in vepu511_h265e_save_pass1_patch()
689 reg_frm->common.enc_pic.slen_fifo = 0; in vepu511_h265e_save_pass1_patch()
697 H265eVepu511Frame *reg_frm = &regs->reg_frm; in vepu511_h265e_use_pass1_patch() local
706 reg_frm->common.enc_pic.rfpr_compress_mode = 1; in vepu511_h265e_use_pass1_patch()
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H A Dhal_h265e_vepu510_tune.c157 H265eVepu510Frame *reg_frm = &regs->reg_frm; in vepu510_h265e_tune_qpmap_init() local
181 reg_frm->common.adr_roir = roir_buf_fd; in vepu510_h265e_tune_qpmap_init()
H A Dhal_h265e_vepu510_reg.h809 H265eVepu510Frame reg_frm; member
H A Dhal_h265e_vepu511_reg.h1561 H265eVepu511Frame reg_frm; member