Lines Matching refs:reg_frm
701 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_prep() local
715 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu510_prep()
716 reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu510_prep()
717 reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu510_prep()
718 reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu510_prep()
722 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu510_prep()
723 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu510_prep()
724 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu510_prep()
725 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu510_prep()
789 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu510_prep()
790 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu510_prep()
791 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu510_prep()
793 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu510_prep()
794 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu510_prep()
795 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu510_prep()
797 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu510_prep()
798 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu510_prep()
799 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu510_prep()
801 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu510_prep()
802 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu510_prep()
803 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu510_prep()
807 reg_frm->common.src_udfy.csc_wgt_b2y = cfg.weight[0]; in setup_vepu510_prep()
808 reg_frm->common.src_udfy.csc_wgt_g2y = cfg.weight[1]; in setup_vepu510_prep()
809 reg_frm->common.src_udfy.csc_wgt_r2y = cfg.weight[2]; in setup_vepu510_prep()
811 reg_frm->common.src_udfu.csc_wgt_b2u = cfg.weight[3]; in setup_vepu510_prep()
812 reg_frm->common.src_udfu.csc_wgt_g2u = cfg.weight[4]; in setup_vepu510_prep()
813 reg_frm->common.src_udfu.csc_wgt_r2u = cfg.weight[5]; in setup_vepu510_prep()
815 reg_frm->common.src_udfv.csc_wgt_b2v = cfg.weight[6]; in setup_vepu510_prep()
816 reg_frm->common.src_udfv.csc_wgt_g2v = cfg.weight[7]; in setup_vepu510_prep()
817 reg_frm->common.src_udfv.csc_wgt_r2v = cfg.weight[8]; in setup_vepu510_prep()
819 reg_frm->common.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu510_prep()
820 reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu510_prep()
821 reg_frm->common.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu510_prep()
824 reg_frm->common.src_strd0.src_strd0 = y_stride; in setup_vepu510_prep()
825 reg_frm->common.src_strd1.src_strd1 = c_stride; in setup_vepu510_prep()
827 reg_frm->common.src_proc.src_mirr = prep->mirroring > 0; in setup_vepu510_prep()
828 reg_frm->common.src_proc.src_rot = prep->rotation; in setup_vepu510_prep()
831 reg_frm->common.src_proc.tile4x4_en = 1; in setup_vepu510_prep()
833 reg_frm->common.src_proc.tile4x4_en = 0; in setup_vepu510_prep()
835 reg_frm->sli_cfg.mv_v_lmt_thd = 0; in setup_vepu510_prep()
836 reg_frm->sli_cfg.mv_v_lmt_en = 0; in setup_vepu510_prep()
838 reg_frm->common.pic_ofst.pic_ofst_y = 0; in setup_vepu510_prep()
839 reg_frm->common.pic_ofst.pic_ofst_x = 0; in setup_vepu510_prep()
848 H264eVepu510Frame *reg_frm = ®s->reg_frm; in vepu510_h264e_save_pass1_patch() local
860 reg_frm->common.enc_pic.cur_frm_ref = 1; in vepu510_h264e_save_pass1_patch()
861 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); in vepu510_h264e_save_pass1_patch()
862 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr; in vepu510_h264e_save_pass1_patch()
863 reg_frm->common.enc_pic.rec_fbc_dis = 1; in vepu510_h264e_save_pass1_patch()
868 reg_frm->common.sli_splt.sli_splt = 0; in vepu510_h264e_save_pass1_patch()
869 reg_frm->common.enc_pic.slen_fifo = 0; in vepu510_h264e_save_pass1_patch()
877 H264eVepu510Frame *reg_frm = ®s->reg_frm; in vepu510_h264e_use_pass1_patch() local
884 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu510_h264e_use_pass1_patch()
885 reg_frm->common.src_fmt.alpha_swap = 0; in vepu510_h264e_use_pass1_patch()
886 reg_frm->common.src_fmt.rbuv_swap = 0; in vepu510_h264e_use_pass1_patch()
887 reg_frm->common.src_fmt.out_fmt = 1; in vepu510_h264e_use_pass1_patch()
888 reg_frm->common.src_fmt.src_rcne = 1; in vepu510_h264e_use_pass1_patch()
892 reg_frm->common.src_strd0.src_strd0 = y_stride; in vepu510_h264e_use_pass1_patch()
893 reg_frm->common.src_strd1.src_strd1 = 3 * c_stride; in vepu510_h264e_use_pass1_patch()
895 reg_frm->common.src_proc.src_mirr = 0; in vepu510_h264e_use_pass1_patch()
896 reg_frm->common.src_proc.src_rot = 0; in vepu510_h264e_use_pass1_patch()
898 reg_frm->common.pic_ofst.pic_ofst_y = 0; in vepu510_h264e_use_pass1_patch()
899 reg_frm->common.pic_ofst.pic_ofst_x = 0; in vepu510_h264e_use_pass1_patch()
902 reg_frm->common.adr_src0 = fd_in; in vepu510_h264e_use_pass1_patch()
903 reg_frm->common.adr_src1 = fd_in; in vepu510_h264e_use_pass1_patch()
904 reg_frm->common.adr_src2 = fd_in; in vepu510_h264e_use_pass1_patch()
915 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_codec() local
919 reg_frm->common.enc_pic.enc_stnd = 0; in setup_vepu510_codec()
920 reg_frm->common.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; in setup_vepu510_codec()
921 reg_frm->common.enc_pic.bs_scp = 1; in setup_vepu510_codec()
923 reg_frm->synt_nal.nal_ref_idc = slice->nal_reference_idc; in setup_vepu510_codec()
924 reg_frm->synt_nal.nal_unit_type = slice->nalu_type; in setup_vepu510_codec()
926 reg_frm->synt_sps.max_fnum = sps->log2_max_frame_num_minus4; in setup_vepu510_codec()
927 reg_frm->synt_sps.drct_8x8 = sps->direct8x8_inference; in setup_vepu510_codec()
928 reg_frm->synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; in setup_vepu510_codec()
929 reg_frm->synt_sps.poc_type = sps->pic_order_cnt_type; in setup_vepu510_codec()
931 reg_frm->synt_pps.etpy_mode = pps->entropy_coding_mode; in setup_vepu510_codec()
932 reg_frm->synt_pps.trns_8x8 = pps->transform_8x8_mode; in setup_vepu510_codec()
933 reg_frm->synt_pps.csip_flag = pps->constrained_intra_pred; in setup_vepu510_codec()
934 reg_frm->synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; in setup_vepu510_codec()
935 reg_frm->synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; in setup_vepu510_codec()
936 reg_frm->synt_pps.pic_init_qp = pps->pic_init_qp; in setup_vepu510_codec()
937 reg_frm->synt_pps.cb_ofst = pps->chroma_qp_index_offset; in setup_vepu510_codec()
938 reg_frm->synt_pps.cr_ofst = pps->second_chroma_qp_index_offset; in setup_vepu510_codec()
939 reg_frm->synt_pps.dbf_cp_flg = pps->deblocking_filter_control; in setup_vepu510_codec()
941 reg_frm->synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); in setup_vepu510_codec()
942 reg_frm->synt_sli0.pps_id = slice->pic_parameter_set_id; in setup_vepu510_codec()
943 reg_frm->synt_sli0.drct_smvp = 0; in setup_vepu510_codec()
944 reg_frm->synt_sli0.num_ref_ovrd = slice->num_ref_idx_override; in setup_vepu510_codec()
945 reg_frm->synt_sli0.cbc_init_idc = slice->cabac_init_idc; in setup_vepu510_codec()
946 reg_frm->synt_sli0.frm_num = slice->frame_num; in setup_vepu510_codec()
948 …reg_frm->synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_… in setup_vepu510_codec()
949 reg_frm->synt_sli1.poc_lsb = slice->pic_order_cnt_lsb; in setup_vepu510_codec()
952 reg_frm->synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc; in setup_vepu510_codec()
953 reg_frm->synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu510_codec()
961 reg_frm->synt_sli2.ref_list0_rodr = 1; in setup_vepu510_codec()
962 reg_frm->synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; in setup_vepu510_codec()
967 reg_frm->synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; in setup_vepu510_codec()
970 reg_frm->synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx; in setup_vepu510_codec()
979 reg_frm->synt_sli2.ref_list0_rodr = 0; in setup_vepu510_codec()
980 reg_frm->synt_sli2.rodr_pic_idx = 0; in setup_vepu510_codec()
981 reg_frm->synt_sli2.rodr_pic_num = 0; in setup_vepu510_codec()
986 reg_frm->synt_refm0.nopp_flg = 0; in setup_vepu510_codec()
987 reg_frm->synt_refm0.ltrf_flg = 0; in setup_vepu510_codec()
988 reg_frm->synt_refm0.arpm_flg = 0; in setup_vepu510_codec()
989 reg_frm->synt_refm0.mmco4_pre = 0; in setup_vepu510_codec()
990 reg_frm->synt_refm0.mmco_type0 = 0; in setup_vepu510_codec()
991 reg_frm->synt_refm0.mmco_parm0 = 0; in setup_vepu510_codec()
992 reg_frm->synt_refm0.mmco_type1 = 0; in setup_vepu510_codec()
993 reg_frm->synt_refm1.mmco_parm1 = 0; in setup_vepu510_codec()
994 reg_frm->synt_refm0.mmco_type2 = 0; in setup_vepu510_codec()
995 reg_frm->synt_refm1.mmco_parm2 = 0; in setup_vepu510_codec()
996 reg_frm->synt_refm2.long_term_frame_idx0 = 0; in setup_vepu510_codec()
997 reg_frm->synt_refm2.long_term_frame_idx1 = 0; in setup_vepu510_codec()
998 reg_frm->synt_refm2.long_term_frame_idx2 = 0; in setup_vepu510_codec()
1004 reg_frm->synt_refm0.nopp_flg = slice->no_output_of_prior_pics; in setup_vepu510_codec()
1005 reg_frm->synt_refm0.ltrf_flg = slice->long_term_reference_flag; in setup_vepu510_codec()
1010 reg_frm->synt_refm0.arpm_flg = 1; in setup_vepu510_codec()
1045 reg_frm->synt_refm0.mmco_type0 = type; in setup_vepu510_codec()
1046 reg_frm->synt_refm0.mmco_parm0 = param_0; in setup_vepu510_codec()
1047 reg_frm->synt_refm2.long_term_frame_idx0 = param_1; in setup_vepu510_codec()
1081 reg_frm->synt_refm0.mmco_type1 = type; in setup_vepu510_codec()
1082 reg_frm->synt_refm1.mmco_parm1 = param_0; in setup_vepu510_codec()
1083 reg_frm->synt_refm2.long_term_frame_idx1 = param_1; in setup_vepu510_codec()
1117 reg_frm->synt_refm0.mmco_type2 = type; in setup_vepu510_codec()
1118 reg_frm->synt_refm1.mmco_parm2 = param_0; in setup_vepu510_codec()
1119 reg_frm->synt_refm2.long_term_frame_idx2 = param_1; in setup_vepu510_codec()
1131 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_rdo_pred() local
1142 reg_frm->rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && in setup_vepu510_rdo_pred()
1144 reg_frm->rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && in setup_vepu510_rdo_pred()
1146 reg_frm->rdo_cfg.chrm_spcl = 1; in setup_vepu510_rdo_pred()
1147 reg_frm->rdo_cfg.ccwa_e = 1; in setup_vepu510_rdo_pred()
1148 reg_frm->rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present; in setup_vepu510_rdo_pred()
1149 reg_frm->rdo_cfg.atf_e = ctx->cfg->tune.anti_flicker_str > 0; in setup_vepu510_rdo_pred()
1150 reg_frm->rdo_cfg.atr_e = ctx->cfg->tune.atr_str_i > 0; in setup_vepu510_rdo_pred()
1151 reg_frm->rdo_cfg.atr_mult_sel_e = 1; in setup_vepu510_rdo_pred()
1152 reg_frm->iprd_csts.rdo_mark_mode = 0; in setup_vepu510_rdo_pred()
1165 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_rc_base() local
1204 reg_frm->common.enc_pic.pic_qp = rc_info->quality_target; in setup_vepu510_rc_base()
1205 reg_frm->common.rc_qp.rc_max_qp = rc_info->quality_target; in setup_vepu510_rc_base()
1206 reg_frm->common.rc_qp.rc_min_qp = rc_info->quality_target; in setup_vepu510_rc_base()
1218 reg_frm->common.enc_pic.pic_qp = qp_target; in setup_vepu510_rc_base()
1220 reg_frm->common.rc_cfg.rc_en = 1; in setup_vepu510_rc_base()
1221 reg_frm->common.rc_cfg.aq_en = 1; in setup_vepu510_rc_base()
1222 reg_frm->common.rc_cfg.rc_ctu_num = mb_w; in setup_vepu510_rc_base()
1224 reg_frm->common.rc_qp.rc_max_qp = qp_max; in setup_vepu510_rc_base()
1225 reg_frm->common.rc_qp.rc_min_qp = qp_min; in setup_vepu510_rc_base()
1226 reg_frm->common.rc_tgt.ctu_ebit = mb_target_bits_mul_16; in setup_vepu510_rc_base()
1229 reg_frm->common.rc_qp.rc_qp_range = 0; in setup_vepu510_rc_base()
1231 reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? in setup_vepu510_rc_base()
1248 reg_frm->common.enc_pic.pic_qp = fqp_min; in setup_vepu510_rc_base()
1249 reg_frm->common.rc_qp.rc_qp_range = 0; in setup_vepu510_rc_base()
1284 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_io_buf() local
1295 reg_frm->common.adr_src0 = fd_in; in setup_vepu510_io_buf()
1296 reg_frm->common.adr_src1 = fd_in; in setup_vepu510_io_buf()
1297 reg_frm->common.adr_src2 = fd_in; in setup_vepu510_io_buf()
1299 reg_frm->common.bsbt_addr = fd_out; in setup_vepu510_io_buf()
1300 reg_frm->common.bsbb_addr = fd_out; in setup_vepu510_io_buf()
1301 reg_frm->common.adr_bsbs = fd_out; in setup_vepu510_io_buf()
1302 reg_frm->common.bsbr_addr = fd_out; in setup_vepu510_io_buf()
1304 reg_frm->common.rfpt_h_addr = 0xffffffff; in setup_vepu510_io_buf()
1305 reg_frm->common.rfpb_h_addr = 0; in setup_vepu510_io_buf()
1306 reg_frm->common.rfpt_b_addr = 0xffffffff; in setup_vepu510_io_buf()
1307 reg_frm->common.adr_rfpb_b = 0; in setup_vepu510_io_buf()
1418 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_intra_refresh() local
1467 reg_frm->common.me_rnge.cime_srch_uph = 1; in setup_vepu510_intra_refresh()
1478 reg_frm->common.me_rnge.cime_srch_dwnh = 1; in setup_vepu510_intra_refresh()
1498 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_recn_refr() local
1517 reg_frm->common.rfpw_h_addr = fd; in setup_vepu510_recn_refr()
1518 reg_frm->common.rfpw_b_addr = fd; in setup_vepu510_recn_refr()
1519 reg_frm->common.dspw_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu510_recn_refr()
1520 reg_frm->common.adr_smear_wr = mpp_buffer_get_fd(buf_smear); in setup_vepu510_recn_refr()
1532 reg_frm->common.rfpr_h_addr = fd; in setup_vepu510_recn_refr()
1533 reg_frm->common.rfpr_b_addr = fd; in setup_vepu510_recn_refr()
1534 reg_frm->common.dspr_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu510_recn_refr()
1535 reg_frm->common.adr_smear_rd = mpp_buffer_get_fd(buf_smear); in setup_vepu510_recn_refr()
1545 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_split() local
1552 reg_frm->common.sli_splt.sli_splt = 0; in setup_vepu510_split()
1553 reg_frm->common.sli_splt.sli_splt_mode = 0; in setup_vepu510_split()
1554 reg_frm->common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1555 reg_frm->common.sli_splt.sli_max_num_m1 = 0; in setup_vepu510_split()
1556 reg_frm->common.sli_splt.sli_flsh = 0; in setup_vepu510_split()
1557 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu510_split()
1559 reg_frm->common.sli_byte.sli_splt_byte = 0; in setup_vepu510_split()
1560 reg_frm->common.enc_pic.slen_fifo = 0; in setup_vepu510_split()
1563 reg_frm->common.sli_splt.sli_splt = 1; in setup_vepu510_split()
1564 reg_frm->common.sli_splt.sli_splt_mode = 0; in setup_vepu510_split()
1565 reg_frm->common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1566 reg_frm->common.sli_splt.sli_max_num_m1 = 500; in setup_vepu510_split()
1567 reg_frm->common.sli_splt.sli_flsh = 1; in setup_vepu510_split()
1568 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu510_split()
1570 reg_frm->common.sli_byte.sli_splt_byte = cfg->split_arg; in setup_vepu510_split()
1571 reg_frm->common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu510_split()
1572 regs->reg_ctl.int_en.vslc_done_en = reg_frm->common.enc_pic.slen_fifo; in setup_vepu510_split()
1579 reg_frm->common.sli_splt.sli_splt = 1; in setup_vepu510_split()
1580 reg_frm->common.sli_splt.sli_splt_mode = 1; in setup_vepu510_split()
1581 reg_frm->common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1582 reg_frm->common.sli_splt.sli_max_num_m1 = 500; in setup_vepu510_split()
1583 reg_frm->common.sli_splt.sli_flsh = 1; in setup_vepu510_split()
1584 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; in setup_vepu510_split()
1586 reg_frm->common.sli_byte.sli_splt_byte = 0; in setup_vepu510_split()
1587 reg_frm->common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu510_split()
1589 (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN))) in setup_vepu510_split()
1603 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_me() local
1609 reg_frm->common.me_rnge.cime_srch_dwnh = 15; in setup_vepu510_me()
1610 reg_frm->common.me_rnge.cime_srch_uph = 15; in setup_vepu510_me()
1611 reg_frm->common.me_rnge.cime_srch_rgtw = 12; in setup_vepu510_me()
1612 reg_frm->common.me_rnge.cime_srch_lftw = 12; in setup_vepu510_me()
1613 reg_frm->common.me_cfg.rme_srch_h = 3; in setup_vepu510_me()
1614 reg_frm->common.me_cfg.rme_srch_v = 3; in setup_vepu510_me()
1616 reg_frm->common.me_cfg.srgn_max_num = 54; in setup_vepu510_me()
1617 reg_frm->common.me_cfg.cime_dist_thre = 1024; in setup_vepu510_me()
1618 reg_frm->common.me_cfg.rme_dis = 0; in setup_vepu510_me()
1619 reg_frm->common.me_cfg.fme_dis = 0; in setup_vepu510_me()
1620 reg_frm->common.me_rnge.dlt_frm_num = 0x0; in setup_vepu510_me()
1621 reg_frm->common.me_cach.cime_zero_thre = 64; in setup_vepu510_me()
1748 H264eVepu510Frame *reg_frm = ®s->reg_frm; in setup_vepu510_ext_line_buf() local
1754 reg_frm->common.ebufb_addr = 0; in setup_vepu510_ext_line_buf()
1755 reg_frm->common.ebufb_addr = 0; in setup_vepu510_ext_line_buf()
1762 reg_frm->common.ebuft_addr = fd; in setup_vepu510_ext_line_buf()
1763 reg_frm->common.ebufb_addr = fd; in setup_vepu510_ext_line_buf()
1781 H264eVepu510Frame *reg_frm = &ctx->regs_set->reg_frm; in setup_vepu510_dual_core() local
1795 reg_frm->common.dual_core.dchs_txid = ctx->curr_idx; in setup_vepu510_dual_core()
1796 reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx; in setup_vepu510_dual_core()
1797 reg_frm->common.dual_core.dchs_txe = 1; in setup_vepu510_dual_core()
1798 reg_frm->common.dual_core.dchs_rxe = dchs_rxe; in setup_vepu510_dual_core()
1799 reg_frm->common.dual_core.dchs_ofst = dchs_ofst; in setup_vepu510_dual_core()
1800 reg_frm->common.dual_core.dchs_dly = dchs_dly; in setup_vepu510_dual_core()
2161 H264eVepu510Frame *reg_frm = ®s->reg_frm; in hal_h264e_vepu510_gen_regs() local
2196 reg_frm->common.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; in hal_h264e_vepu510_gen_regs()
2197 reg_frm->common.enc_pic.mei_stor = task->md_info ? 1 : 0; in hal_h264e_vepu510_gen_regs()
2199 reg_frm->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in hal_h264e_vepu510_gen_regs()
2200 reg_frm->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in hal_h264e_vepu510_gen_regs()
2262 wr_cfg.reg = ®s->reg_frm; in hal_h264e_vepu510_start()
2263 wr_cfg.size = sizeof(regs->reg_frm); in hal_h264e_vepu510_start()