Searched refs:reg16 (Results 1 – 18 of 18) sorted by relevance
60 reg->reg16.sw_ac1_code1_cnt = ac_ptr0->bits[0]; in jpegd_write_code_word_number()61 reg->reg16.sw_ac1_code2_cnt = ac_ptr0->bits[1]; in jpegd_write_code_word_number()62 reg->reg16.sw_ac1_code3_cnt = ac_ptr0->bits[2]; in jpegd_write_code_word_number()63 reg->reg16.sw_ac1_code4_cnt = ac_ptr0->bits[3]; in jpegd_write_code_word_number()64 reg->reg16.sw_ac1_code5_cnt = ac_ptr0->bits[4]; in jpegd_write_code_word_number()65 reg->reg16.sw_ac1_code6_cnt = ac_ptr0->bits[5]; in jpegd_write_code_word_number()
530 reg->reg16.sw_rgb_r_padd = cfg->r_padd; in jpegd_setup_pp()531 reg->reg16.sw_rgb_g_padd = cfg->g_padd; in jpegd_setup_pp()532 reg->reg16.sw_rgb_b_padd = cfg->b_padd; in jpegd_setup_pp()
410 } reg16; member
105 } reg16; member
749 dmsr->reg16.sw_dmsr_diff_coring_y0 = diff_coring_y0; in set_dmsr_to_vdpp_reg()750 dmsr->reg16.sw_dmsr_diff_coring_y1 = diff_coring_y1; in set_dmsr_to_vdpp_reg()917 zme->common.reg16.cbcr_xscl_factor = cbcr_scl_info.xscl_factor; in set_zme_to_vdpp_reg()918 zme->common.reg16.cbcr_xscl_offset = cbcr_scl_info.xscl_offset; in set_zme_to_vdpp_reg()
131 RK_U32 reg16; // 0x0040 member
152 } reg16; /* 0x00C0 */ member343 } reg16; /* 0x0040 */ member687 } reg16; /* 0x0240 */ member1031 } reg16; /* 0x0440 */ member1375 } reg16; /* 0x0640 */ member1745 } reg16; /* 0x0840 */ member
158 } reg16; // 0x0040 member331 } reg16; // 0x0140 member489 } reg16; // 0x0240 member
494 dst_reg->es.reg16.conf_mean_th = conf_local_mean_th; in set_es_to_vdpp2_reg()495 dst_reg->es.reg16.conf_cnt_th = p_es_param->es_iConfCntTh; in set_es_to_vdpp2_reg()496 dst_reg->es.reg16.low_conf_th = p_es_param->es_iLowConfTh; in set_es_to_vdpp2_reg()497 dst_reg->es.reg16.low_conf_ratio = p_es_param->es_iLowConfRatio; in set_es_to_vdpp2_reg()672 dst_reg->sharp.reg16.sw_peaking0_value_n1 = peaking_ctrl_value_N1[0]; in set_shp_to_vdpp2_reg()673 dst_reg->sharp.reg16.sw_peaking0_value_n2 = peaking_ctrl_value_N2[0]; in set_shp_to_vdpp2_reg()1169 …dst_reg->common.reg16.sw_vdpp_dst_pic_width_c = src_params->dst_c_width + dst_right_redundant_c - … in vdpp2_params_to_reg()1170 dst_reg->common.reg16.sw_vdpp_dst_right_redundant_c = dst_right_redundant_c; in vdpp2_params_to_reg()1171 dst_reg->common.reg16.sw_vdpp_dst_pic_height_c = src_params->dst_c_height - 1; in vdpp2_params_to_reg()
256 ctrl_regs->reg16.error_proc_disable = 1; in init_ctrl_regs()257 ctrl_regs->reg16.error_spread_disable = 0; in init_ctrl_regs()258 ctrl_regs->reg16.roi_error_ctu_cal_en = 0; in init_ctrl_regs()
565 ctrl_regs->reg16.error_proc_disable = 1; in init_ctrl_regs()566 ctrl_regs->reg16.error_spread_disable = 0; in init_ctrl_regs()567 ctrl_regs->reg16.roi_error_ctu_cal_en = 0; in init_ctrl_regs()
607 ctrl_regs->reg16.error_proc_disable = 1; in init_ctrl_regs()608 ctrl_regs->reg16.error_spread_disable = 0; in init_ctrl_regs()609 ctrl_regs->reg16.roi_error_ctu_cal_en = 0; in init_ctrl_regs()
1030 hw_regs->ctrl_regs.reg16.error_proc_disable = 1; in hal_h265d_vdpu384a_gen_regs()1031 hw_regs->ctrl_regs.reg16.error_spread_disable = 0; in hal_h265d_vdpu384a_gen_regs()1032 hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0; in hal_h265d_vdpu384a_gen_regs()1072 hw_regs->ctrl_regs.reg16.error_proc_disable = 1; in hal_h265d_vdpu384a_gen_regs()
1095 hw_regs->ctrl_regs.reg16.error_proc_disable = 1; in hal_h265d_vdpu383_gen_regs()1096 hw_regs->ctrl_regs.reg16.error_spread_disable = 0; in hal_h265d_vdpu383_gen_regs()1097 hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0; in hal_h265d_vdpu383_gen_regs()1134 hw_regs->ctrl_regs.reg16.error_proc_disable = 1; in hal_h265d_vdpu383_gen_regs()
138 } reg16; member
162 } reg16; member
1034 vp9_hw_regs->ctrl_regs.reg16.error_proc_disable = 1; in hal_vp9d_vdpu383_gen_regs()1035 vp9_hw_regs->ctrl_regs.reg16.error_spread_disable = 0; in hal_vp9d_vdpu383_gen_regs()1036 vp9_hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0; in hal_vp9d_vdpu383_gen_regs()
2251 regs->ctrl_regs.reg16.error_proc_disable = 1; in vdpu383_av1d_gen_regs()2252 regs->ctrl_regs.reg16.error_spread_disable = 0; in vdpu383_av1d_gen_regs()2253 regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0; in vdpu383_av1d_gen_regs()