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Searched refs:reg102 (Results 1 – 10 of 10) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c788 regs->reg102.inter_4x4 = 0; in setup_vepu541_rdo_pred()
789 regs->reg102.rdo_mask = 24; in setup_vepu541_rdo_pred()
790 regs->reg102.atf_intra_e = 1; in setup_vepu541_rdo_pred()
794 regs->reg102.inter_4x4 = 1; in setup_vepu541_rdo_pred()
795 regs->reg102.rdo_mask = 0; in setup_vepu541_rdo_pred()
796 regs->reg102.atf_intra_e = 0; in setup_vepu541_rdo_pred()
799 regs->reg102.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && in setup_vepu541_rdo_pred()
802 regs->reg102.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && in setup_vepu541_rdo_pred()
804 regs->reg102.chrm_spcl = 1; in setup_vepu541_rdo_pred()
805 regs->reg102.ccwa_e = 1; in setup_vepu541_rdo_pred()
[all …]
H A Dhal_h264e_vepu541_reg.h1593 } reg102; member
/rockchip-linux_mpp/mpp/hal/rkdec/inc/
H A Dvdpu34x_h264d.h149 } reg102; member
H A Dvdpu382_h264d.h149 } reg102; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c80 case 12: regs.reg102.ref12_##field = value; break;\
81 case 13: regs.reg102.ref13_##field = value; break;\
82 case 14: regs.reg102.ref14_##field = value; break;\
83 case 15: regs.reg102.ref15_##field = value; break;\
H A Dhal_h264d_vdpu384a.c56 case 12: regs.reg102.ref12_##field = value; break;\
57 case 13: regs.reg102.ref13_##field = value; break;\
58 case 14: regs.reg102.ref14_##field = value; break;\
59 case 15: regs.reg102.ref15_##field = value; break;\
H A Dhal_h264d_vdpu383.c65 case 12: regs.reg102.ref12_##field = value; break;\
66 case 13: regs.reg102.ref13_##field = value; break;\
67 case 14: regs.reg102.ref14_##field = value; break;\
68 case 15: regs.reg102.ref15_##field = value; break;\
H A Dhal_h264d_vdpu382.c82 case 12: regs.reg102.ref12_##field = value; break;\
83 case 13: regs.reg102.ref13_##field = value; break;\
84 case 14: regs.reg102.ref14_##field = value; break;\
85 case 15: regs.reg102.ref15_##field = value; break;\
/rockchip-linux_mpp/mpp/vproc/vdpp/
H A Dvdpp2.c843 … dst_reg->sharp.reg102.sw_diag_adjgain_tab0 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[0]; in set_shp_to_vdpp2_reg()
844 … dst_reg->sharp.reg102.sw_diag_adjgain_tab1 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[1]; in set_shp_to_vdpp2_reg()
845 … dst_reg->sharp.reg102.sw_diag_adjgain_tab2 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[2]; in set_shp_to_vdpp2_reg()
846 … dst_reg->sharp.reg102.sw_diag_adjgain_tab3 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[3]; in set_shp_to_vdpp2_reg()
847 … dst_reg->sharp.reg102.sw_diag_adjgain_tab4 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[4]; in set_shp_to_vdpp2_reg()
848 … dst_reg->sharp.reg102.sw_diag_adjgain_tab5 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[5]; in set_shp_to_vdpp2_reg()
849 … dst_reg->sharp.reg102.sw_diag_adjgain_tab6 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[6]; in set_shp_to_vdpp2_reg()
850 … dst_reg->sharp.reg102.sw_diag_adjgain_tab7 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[7]; in set_shp_to_vdpp2_reg()
H A Dvdpp2_reg.h915 } reg102; // 0x0398 member