Searched refs:reg0196_enc_rsl (Results 1 – 5 of 5) sorted by relevance
464 } reg0196_enc_rsl; member
471 } reg0196_enc_rsl; member
958 RK_S32 pic_wdt_align = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 31) / 32 ; in vepu540c_h265_set_me_regs()1261 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v540c_gen_regs()1264 reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; in hal_h265e_v540c_gen_regs()
268 RK_U32 pic_wd64 = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64; in vepu580_h265_set_me_ram()2742 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v580_gen_regs()2745 reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; in hal_h265e_v580_gen_regs()
354 } reg0196_enc_rsl; member