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Searched refs:offset_spspps (Results 1 – 9 of 9) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_ctx.h84 RK_U32 offset_spspps[MAX_GEN_REG]; member
H A Dhal_h265d_vdpu382.c143 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu382_init()
151 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu382_init()
680 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu382_gen_regs()
H A Dhal_h265d_vdpu384a.c132 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu384a_init()
141 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu384a_init()
810 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu384a_gen_regs()
H A Dhal_h265d_vdpu34x.c145 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu34x_init()
153 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu34x_init()
874 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu34x_gen_regs()
H A Dhal_h265d_vdpu383.c155 reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i); in hal_h265d_vdpu383_init()
165 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in hal_h265d_vdpu383_init()
890 reg_ctx->spspps_offset = reg_ctx->offset_spspps[i]; in hal_h265d_vdpu383_gen_regs()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c142 RK_U32 offset_spspps[VDPU34X_FAST_REG_SET_CNT]; member
730 reg_ctx->offset_spspps[i] = VDPU34X_SPSPPS_OFFSET(i); in vdpu34x_h264d_init()
737 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in vdpu34x_h264d_init()
944 ctx->spspps_offset = ctx->offset_spspps[i]; in vdpu34x_h264d_gen_regs()
H A Dhal_h264d_vdpu384a.c78 RK_U32 offset_spspps[VDPU384A_FAST_REG_SET_CNT]; member
609 reg_ctx->offset_spspps[i] = VDPU384A_SPSPPS_OFFSET(i); in vdpu384a_h264d_init()
617 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in vdpu384a_h264d_init()
817 ctx->spspps_offset = ctx->offset_spspps[i]; in vdpu384a_h264d_gen_regs()
H A Dhal_h264d_vdpu383.c89 RK_U32 offset_spspps[VDPU383_FAST_REG_SET_CNT]; member
652 reg_ctx->offset_spspps[i] = VDPU383_SPSPPS_OFFSET(i); in vdpu383_h264d_init()
661 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in vdpu383_h264d_init()
865 ctx->spspps_offset = ctx->offset_spspps[i]; in vdpu383_h264d_gen_regs()
H A Dhal_h264d_vdpu382.c146 RK_U32 offset_spspps[VDPU382_FAST_REG_SET_CNT]; member
751 reg_ctx->offset_spspps[i] = VDPU382_SPSPPS_OFFSET(i); in vdpu382_h264d_init()
758 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0]; in vdpu382_h264d_init()
973 ctx->spspps_offset = ctx->offset_spspps[i]; in vdpu382_h264d_gen_regs()