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Searched refs:mpp_dev_multi_offset_update (Results 1 – 10 of 10) sorted by relevance

/rockchip-linux_mpp/osal/inc/
H A Dmpp_device.h170 MPP_RET mpp_dev_multi_offset_update(MppDevRegOffCfgs *cfgs, RK_S32 index, RK_U32 offset);
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu580_common.c78 … mpp_dev_multi_offset_update(reg_cfg, VEPU580_OSD_ADDR_IDX_BASE + k, tmp->buf_offset); in vepu580_set_osd()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu580.c844 mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align); in vepu580_h264e_save_pass1_patch()
884 mpp_dev_multi_offset_update(ctx->offsets, 161, frame_size); in vepu580_h264e_use_pass1_patch()
885 mpp_dev_multi_offset_update(ctx->offsets, 162, frame_size); in vepu580_h264e_use_pass1_patch()
1427 mpp_dev_multi_offset_update(offsets, 161, off_in[0]); in setup_vepu580_io_buf()
1428 mpp_dev_multi_offset_update(offsets, 162, off_in[1]); in setup_vepu580_io_buf()
1429 mpp_dev_multi_offset_update(offsets, 172, siz_out); in setup_vepu580_io_buf()
1430 mpp_dev_multi_offset_update(offsets, 175, off_out); in setup_vepu580_io_buf()
1664 mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size); in setup_vepu580_recn_refr()
1665 mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size); in setup_vepu580_recn_refr()
2068 mpp_dev_multi_offset_update(ctx->offsets, 182, offset); in setup_vepu580_ext_line_buf()
H A Dhal_h264e_vepu510.c865 mpp_dev_multi_offset_update(ctx->offsets, 164, 0); in vepu510_h264e_save_pass1_patch()
906 mpp_dev_multi_offset_update(ctx->offsets, 161, 2 * y_stride); in vepu510_h264e_use_pass1_patch()
1354 mpp_dev_multi_offset_update(offsets, 161, off_in[0]); in setup_vepu510_io_buf()
1355 mpp_dev_multi_offset_update(offsets, 162, off_in[1]); in setup_vepu510_io_buf()
1356 mpp_dev_multi_offset_update(offsets, 172, siz_out); in setup_vepu510_io_buf()
1357 mpp_dev_multi_offset_update(offsets, 174, off_out); in setup_vepu510_io_buf()
1537 mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size); in setup_vepu510_recn_refr()
1538 mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size); in setup_vepu510_recn_refr()
1765 mpp_dev_multi_offset_update(ctx->offsets, 178, offset); in setup_vepu510_ext_line_buf()
H A Dhal_h264e_vepu511.c837 mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align); in vepu511_h264e_save_pass1_patch()
874 mpp_dev_multi_offset_update(ctx->offsets, 161, width_align * height_align); in vepu511_h264e_use_pass1_patch()
1349 mpp_dev_multi_offset_update(offsets, 161, off_in[0]); in setup_vepu511_io_buf()
1350 mpp_dev_multi_offset_update(offsets, 162, off_in[1]); in setup_vepu511_io_buf()
1351 mpp_dev_multi_offset_update(offsets, 172, siz_out); in setup_vepu511_io_buf()
1352 mpp_dev_multi_offset_update(offsets, 174, off_out); in setup_vepu511_io_buf()
1537 mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size); in setup_vepu511_recn_refr()
1538 mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size); in setup_vepu511_recn_refr()
1757 mpp_dev_multi_offset_update(ctx->offsets, 178, offset); in setup_vepu511_ext_line_buf()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu580.c1690 ret = mpp_dev_multi_offset_update(cfgs, 161, u_offset); in vepu580_h265_set_patch_info()
1695 ret = mpp_dev_multi_offset_update(cfgs, 162, v_offset); in vepu580_h265_set_patch_info()
2466 mpp_dev_multi_offset_update(frm->reg_cfg, 164, ctx->fbc_header_len); in vepu580_h265_set_hw_address()
2475 mpp_dev_multi_offset_update(frm->reg_cfg, 166, ctx->fbc_header_len); in vepu580_h265_set_hw_address()
2529 mpp_dev_multi_offset_update(frm->reg_cfg, 175, mpp_packet_get_length(task->packet)); in vepu580_h265_set_hw_address()
2530 mpp_dev_multi_offset_update(frm->reg_cfg, 172, mpp_buffer_get_size(enc_task->output)); in vepu580_h265_set_hw_address()
2562 mpp_dev_multi_offset_update(frm->reg_cfg, 164, width_align * height_align); in vepu580_h265e_save_pass1_patch()
2599 ret = mpp_dev_multi_offset_update(frm->reg_cfg, 161, frame_size); in vepu580_h265e_use_pass1_patch()
2604 ret = mpp_dev_multi_offset_update(frm->reg_cfg, 162, frame_size); in vepu580_h265e_use_pass1_patch()
2922 mpp_dev_multi_offset_update(frm->reg_cfg, 175, offset); in hal_h265e_v580_start()
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H A Dhal_h265e_vepu510.c1260 mpp_dev_multi_offset_update(offsets, 161, u_offset); in vepu510_h265_set_patch_info()
1261 mpp_dev_multi_offset_update(offsets, 162, v_offset); in vepu510_h265_set_patch_info()
1642 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len); in vepu510_h265_set_hw_address()
1651 mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len); in vepu510_h265_set_hw_address()
1672 mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet)); in vepu510_h265_set_hw_address()
1673 mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output)); in vepu510_h265_set_hw_address()
1708 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, 0); in vepu510_h265e_save_pass1_patch()
1745 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, 2 * hor_stride); in vepu510_h265e_use_pass1_patch()
1765 mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size); in setup_vepu510_ext_line_buf()
H A Dhal_h265e_vepu511.c654 mpp_dev_multi_offset_update(offsets, 161, u_offset); in vepu511_h265_set_patch_info()
655 mpp_dev_multi_offset_update(offsets, 162, v_offset); in vepu511_h265_set_patch_info()
685 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height_align); in vepu511_h265e_save_pass1_patch()
723 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, width_align * height_align); in vepu511_h265e_use_pass1_patch()
740 mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size); in setup_vepu511_ext_line_buf()
1104 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len); in vepu511_h265_set_hw_address()
1113 mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len); in vepu511_h265_set_hw_address()
1135 mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet)); in vepu511_h265_set_hw_address()
1136 mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output)); in vepu511_h265_set_hw_address()
/rockchip-linux_mpp/osal/driver/
H A Dmpp_device.c237 MPP_RET mpp_dev_multi_offset_update(MppDevRegOffCfgs *cfgs, RK_S32 index, RK_U32 offset) in mpp_dev_multi_offset_update() function
/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu2_v2.c685 mpp_dev_multi_offset_update(reg_cfg, VEPU2_REG_INPUT_Y, cfg.offset_byte[0]); in multi_core_start()
686 mpp_dev_multi_offset_update(reg_cfg, VEPU2_REG_INPUT_U, cfg.offset_byte[1]); in multi_core_start()
687 mpp_dev_multi_offset_update(reg_cfg, VEPU2_REG_INPUT_V, cfg.offset_byte[2]); in multi_core_start()