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Searched refs:height_align (Results 1 – 7 of 7) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_base.c993 RK_S32 height_align = MPP_ALIGN(set->height, 16); in set_parameter() local
1010 MPP_SWAP(RK_S32, width_align, height_align); in set_parameter()
1016 ctx->mb_per_frame = width_align / 16 * height_align / 16; in set_parameter()
1018 ctx->mb_per_col = height_align / 16; in set_parameter()
1021 sps->pic_height_in_pixel = height_align; in set_parameter()
1023 sps->pic_height_in_mbs = height_align / 16; in set_parameter()
1106 hw_cfg->mbs_in_col = height_align / 16; in set_parameter()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu511.c822 RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16); in vepu511_h264e_save_pass1_patch() local
825 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu511_h264e_save_pass1_patch()
837 mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align); in vepu511_h264e_save_pass1_patch()
851 RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16); in vepu511_h264e_use_pass1_patch() local
874 mpp_dev_multi_offset_update(ctx->offsets, 161, width_align * height_align); in vepu511_h264e_use_pass1_patch()
H A Dhal_h264e_vepu580.c829 RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16); in vepu580_h264e_save_pass1_patch() local
832 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu580_h264e_save_pass1_patch()
844 mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align); in vepu580_h264e_save_pass1_patch()
H A Dhal_h264e_vepu510.c850 RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16); in vepu510_h264e_save_pass1_patch() local
853 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu510_h264e_save_pass1_patch()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu511.c667 RK_S32 height_align = MPP_ALIGN(height, 16); in vepu511_h265e_save_pass1_patch() local
670 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu511_h265e_save_pass1_patch()
685 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height_align); in vepu511_h265e_save_pass1_patch()
699 RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16); in vepu511_h265e_use_pass1_patch() local
723 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, width_align * height_align); in vepu511_h265e_use_pass1_patch()
H A Dhal_h265e_vepu580.c2544 RK_S32 height_align = MPP_ALIGN(height, 16); in vepu580_h265e_save_pass1_patch() local
2547 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu580_h265e_save_pass1_patch()
2562 mpp_dev_multi_offset_update(frm->reg_cfg, 164, width_align * height_align); in vepu580_h265e_save_pass1_patch()
H A Dhal_h265e_vepu510.c1690 RK_S32 height_align = MPP_ALIGN(height, 16); in vepu510_h265e_save_pass1_patch() local
1693 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2); in vepu510_h265e_save_pass1_patch()