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Searched refs:SwReg03 (Results 1 – 6 of 6) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_vdpu1.c94 regs->SwReg03.sw_dec_mode = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
104 regs->SwReg03.sw_filtering_dis = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
140 regs->SwReg03.sw_pic_b_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
141 regs->SwReg03.sw_pic_inter_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
167 regs->SwReg03.sw_write_mvs_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
174 regs->SwReg03.sw_pic_b_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
175 regs->SwReg03.sw_pic_inter_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
189 regs->SwReg03.sw_write_mvs_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
193 regs->SwReg03.sw_pic_b_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
194 regs->SwReg03.sw_pic_inter_e = 0; in vdpu1_mpg4d_setup_regs_by_syntax()
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H A Dhal_m4vd_vdpu1_reg.h89 } SwReg03; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu1.c355 p_regs->SwReg03.sw_dec_out_dis = 0; in vdpu1_set_vlc_regs()
356 p_regs->SwReg03.sw_rlc_mode_e = 0; in vdpu1_set_vlc_regs()
420 p_regs->SwReg03.sw_picord_count_e = 1; in vdpu1_set_vlc_regs()
598 p_regs->SwReg03.sw_pic_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E in vdpu1_set_asic_regs()
599 p_regs->SwReg03.sw_filtering_dis = 0; in vdpu1_set_asic_regs()
632 p_regs->SwReg03.sw_write_mvs_e = (p_long->nal_ref_idc != 0) ? 1 : 0; /* defalut set 1 */ in vdpu1_set_asic_regs()
639 p_regs->SwReg03.sw_pic_interlace_e = in vdpu1_set_asic_regs()
642 p_regs->SwReg03.sw_pic_fieldmode_e = pp->field_pic_flag; in vdpu1_set_asic_regs()
643 p_regs->SwReg03.sw_pic_topfield_e = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; /* bottomFieldFlag */ in vdpu1_set_asic_regs()
644 p_regs->SwReg03.sw_seq_mbaff_e = pp->MbaffFrameFlag; in vdpu1_set_asic_regs()
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H A Dhal_h264d_vdpu1_reg.h90 } SwReg03; member
/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu1.c66 regs->SwReg03.sw_dec_mode = 2; in vpu1_h263d_setup_regs_by_syntax()
67 regs->SwReg03.sw_filtering_dis = 1; in vpu1_h263d_setup_regs_by_syntax()
96 regs->SwReg03.sw_pic_inter_e = 1; in vpu1_h263d_setup_regs_by_syntax()
107 regs->SwReg03.sw_pic_inter_e = 0; in vpu1_h263d_setup_regs_by_syntax()
H A Dhal_h263d_vdpu1_reg.h88 } SwReg03; member