Lines Matching refs:SwReg03

355     p_regs->SwReg03.sw_dec_out_dis = 0;  in vdpu1_set_vlc_regs()
356     p_regs->SwReg03.sw_rlc_mode_e = 0;  in vdpu1_set_vlc_regs()
420     p_regs->SwReg03.sw_picord_count_e = 1;  in vdpu1_set_vlc_regs()
598     p_regs->SwReg03.sw_pic_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E  in vdpu1_set_asic_regs()
599     p_regs->SwReg03.sw_filtering_dis = 0;  in vdpu1_set_asic_regs()
632     p_regs->SwReg03.sw_write_mvs_e = (p_long->nal_ref_idc != 0) ? 1 : 0; /* defalut set 1 */  in vdpu1_set_asic_regs()
639     p_regs->SwReg03.sw_pic_interlace_e =  in vdpu1_set_asic_regs()
642     p_regs->SwReg03.sw_pic_fieldmode_e = pp->field_pic_flag;  in vdpu1_set_asic_regs()
643     p_regs->SwReg03.sw_pic_topfield_e = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; /* bottomFieldFlag */  in vdpu1_set_asic_regs()
644     p_regs->SwReg03.sw_seq_mbaff_e = pp->MbaffFrameFlag;  in vdpu1_set_asic_regs()
679     p_regs->SwReg03.sw_dec_out_dis = 0; /* set defalut 0 */  in vdpu1_set_asic_regs()
691     p_reg->SwReg03.sw_dec_mode = 0; /* set H264 mode */  in vdpu1_set_device_regs()
717     p_reg->SwReg03.sw_dec_axi_wr_id = (0x00 & 0xFFU); /* 0-255 */  in vdpu1_set_device_regs()