| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/ |
| H A D | speed.c | 75 int temp, vco = 0, bootmod_ccr, pdr; in setup_5441x_clocks() local
107 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
109 gd->arch.vco_clk = vco; in setup_5441x_clocks()
115 gd->cpu_clk = vco / temp; /* cpu clock */ in setup_5441x_clocks()
116 gd->arch.flb_clk = vco / temp; /* FlexBus clock */ in setup_5441x_clocks()
122 gd->bus_clk = vco / temp; /* bus clock */ in setup_5441x_clocks()
134 int vco = 0, temp, fbtemp, pcrvalue; in setup_5445x_clocks() local
196 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC; in setup_5445x_clocks()
198 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { in setup_5445x_clocks()
205 vco = i * CONFIG_SYS_INPUT_CLKSRC; in setup_5445x_clocks()
[all …]
|
| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf5227x/ |
| H A D | speed.c | 76 int vco, temp, pcrvalue, pfdr; in get_clocks() local
91 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
92 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { in get_clocks()
97 vco = in get_clocks()
101 gd->arch.vco_clk = vco; /* Vco clock */ in get_clocks()
104 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
105 gd->arch.vco_clk = vco; /* Vco clock */ in get_clocks()
114 gd->cpu_clk = vco / temp; /* cpu clock */ in get_clocks()
117 gd->arch.flb_clk = vco / temp; /* flexbus clock */ in get_clocks()
|
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 108 &clock_manager_base->main_pll.vco); in cm_basic_init()
111 &clock_manager_base->per_pll.vco); in cm_basic_init()
114 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
129 readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
130 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
131 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
138 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); in cm_basic_init()
139 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
140 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
195 &clock_manager_base->main_pll.vco); in cm_basic_init()
[all …]
|
| H A D | clock_manager_arria10.c | 956 u32 vco = 0; in cm_get_per_vco_clk_hz() local
978 vco = readl(&clock_manager_base->per_pll.vco1); in cm_get_per_vco_clk_hz()
980 numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK; in cm_get_per_vco_clk_hz()
982 denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & in cm_get_per_vco_clk_hz()
985 vco = src_hz; in cm_get_per_vco_clk_hz()
986 vco /= 1 + denom; in cm_get_per_vco_clk_hz()
987 vco *= 1 + numer; in cm_get_per_vco_clk_hz()
989 return vco; in cm_get_per_vco_clk_hz()
994 u32 src_hz, numer, denom, vco; in cm_get_main_vco_clk_hz() local
1012 vco = readl(&clock_manager_base->main_pll.vco1); in cm_get_main_vco_clk_hz()
[all …]
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/s32v234/ |
| H A D | generic.c | 31 u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0; in get_pllfreq() local
48 vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481); in get_pllfreq()
65 fout = vco / (dfs_mfi + (dfs_mfn / 256)); in get_pllfreq()
67 fout = vco / plldv_rfdphi_div; in get_pllfreq()
75 fout = vco / plldv_rfdphi_div; in get_pllfreq()
|
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/ |
| H A D | clock_manager_gen5.h | 50 u32 vco; member
68 u32 vco; member
85 u32 vco; member
|
| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip-inno-hdmi-phy.c | 891 unsigned long rate, vco, frac; in inno_hdmi_3328_phy_pll_recalc_rate() local
898 vco = parent_rate * nf; in inno_hdmi_3328_phy_pll_recalc_rate()
903 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); in inno_hdmi_3328_phy_pll_recalc_rate()
906 rate = vco / (nd * 5); in inno_hdmi_3328_phy_pll_recalc_rate()
913 rate = vco / (nd * no_b * no_d * 2); in inno_hdmi_3328_phy_pll_recalc_rate()
915 rate = vco / (nd * no_a * no_d * 2); in inno_hdmi_3328_phy_pll_recalc_rate()
1104 u64 vco = parent_rate; in inno_hdmi_rk3528_phy_pll_recalc_rate() local
1108 vco *= nf; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1113 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1116 do_div(vco, nd * 5); in inno_hdmi_rk3528_phy_pll_recalc_rate()
[all …]
|
| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 1068 u32 cf, vco, rounded_rate = frequency; in clock_set_display_rate() local
1075 for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++) in clock_set_display_rate()
1076 vco <<= 1; in clock_set_display_rate()
1078 if (vco < min_vco || vco > max_vco) { in clock_set_display_rate()
1085 best_diff = vco; in clock_set_display_rate()
1094 divn = vco / cf; in clock_set_display_rate()
1098 diff = vco - divn * cf; in clock_set_display_rate()
|
| /rk3399_rockchip-uboot/doc/ |
| H A D | README.m54418twr | 86 CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
|
| /rk3399_rockchip-uboot/board/freescale/m54455evb/ |
| H A D | README | 134 CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
|