Home
last modified time | relevance | path

Searched refs:vals (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/test/py/
H A Dconftest.py227 vals = []
232 vals.append(m.group(1) + ' ' + m.group(2))
234 ids = ['ut_' + s.replace(' ', '_') for s in vals]
235 metafunc.parametrize(fixture_name, vals, ids=ids)
263 vals = []
268 vals = (val, )
272 vals = subconfig.get(fixture_name+ 's', [])
278 ids = [fixture_id(index, val) for (index, val) in enumerate(vals)]
279 metafunc.parametrize(fixture_name, vals, ids=ids)
/rk3399_rockchip-uboot/tools/dtoc/
H A Ddtb_platdata.py471 vals = []
487 vals.append('\t{&%s%s, {%s}}' % (VAL_PREFIX, name,
489 for val in vals:
493 vals.append(get_value(prop.type, val))
496 for i in xrange(0, len(vals), 8):
499 self.buf(', '.join(vals[i:i + 8]))
/rk3399_rockchip-uboot/drivers/clk/uniphier/
H A Dclk-uniphier.h26 unsigned int vals[UNIPHIER_CLK_MAX_NR_MUXS]; member
H A Dclk-uniphier-mio.c37 .vals = { \
H A Dclk-uniphier-core.c81 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_get_rate()
115 val |= mux->vals[best_rate_id]; in uniphier_clk_set_rate()
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c348 u32 vals[4]; in rockchip_combphy_parse_dt() local
377 vals, ARRAY_SIZE(vals))) in rockchip_combphy_parse_dt()
378 regmap_write(priv->pipe_grf, vals[0], in rockchip_combphy_parse_dt()
379 (GENMASK(vals[2], vals[1]) << 16) | vals[3]); in rockchip_combphy_parse_dt()
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_init.c790 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()
792 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
793 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
795 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()
H A Dddr3_hw_training.h313 MV_DRAM_TRAINING_INIT *vals; member
/rk3399_rockchip-uboot/include/
H A Dec_commands.h850 } vals[23]; member