Searched refs:v0pll_hz (Results 1 – 4 of 4) sorted by relevance
198 prate = priv->v0pll_hz; in rk3506_armclk_get_rate()233 div = DIV_ROUND_UP(priv->v0pll_hz, new_rate); in rk3506_armclk_set_rate()234 prate = priv->v0pll_hz; in rk3506_armclk_set_rate()290 prate = priv->v0pll_hz; in rk3506_pll_div_get_rate()324 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_pll_div_set_rate()510 prate = priv->v0pll_hz; in rk3506_sdmmc_get_rate()528 } else if (priv->v0pll_hz % rate == 0) { in rk3506_sdmmc_set_rate()530 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_sdmmc_set_rate()670 prate = priv->v0pll_hz; in rk3506_i2c_get_rate()685 if (priv->v0pll_hz % rate == 0) { in rk3506_i2c_set_rate()[all …]
1247 parent = priv->v0pll_hz; in rk3588_clk_csihost_get_clk()1729 priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_clk_set_rate()
35 ulong v0pll_hz; member
48 ulong v0pll_hz; member