Searched refs:u_int32_t (Results 1 – 10 of 10) sorted by relevance
11 u_int32_t pid12;12 u_int32_t emumgt;13 u_int32_t na1;14 u_int32_t na2;15 u_int32_t tim12;16 u_int32_t tim34;17 u_int32_t prd12;18 u_int32_t prd34;19 u_int32_t tcr;20 u_int32_t tgcr;[all …]
39 u_int32_t rsa_n[ROCHCHIP_RSA_PARAMETER_SIZE];40 u_int32_t rsa_e[ROCHCHIP_RSA_PARAMETER_SIZE];41 u_int32_t rsa_c[ROCHCHIP_RSA_PARAMETER_SIZE];
83 u_int32_t max_rx_len; /* Maximum receive packet length. */84 u_int32_t ctl; /* Control bitfield */156 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)157 #define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
148 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; in nand_davinci_hwcontrol()166 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) in nand_davinci_readecc()168 u_int32_t ecc = 0; in nand_davinci_readecc()178 u_int32_t val; in nand_davinci_enable_hwecc()192 u_int32_t tmp; in nand_davinci_calculate_ecc()227 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | in nand_davinci_correct_data()229 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | in nand_davinci_correct_data()231 u_int32_t diff = ecc_calc ^ ecc_nand; in nand_davinci_correct_data()
53 u_int32_t next; /* Pointer to next descriptor56 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */57 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
150 u_int32_t clkdiv; in davinci_eth_mdio_enable()171 u_int32_t phy_act_state; in davinci_eth_phy_detect()418 u_int32_t clkdiv, cnt, mac_control; in davinci_eth_open()474 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); in davinci_eth_open()533 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); in davinci_eth_open()756 u_int32_t phy_id; in davinci_emac_initialize()
123 u_int32_t clkdiv; in keystone2_mdio_reset()
71 (u_int32_t)di->cookie); in dev_enum_net()
259 (u_int32_t)di->cookie); in dev_enum_stor()
100 typedef __u32 u_int32_t; typedef