| /rk3399_rockchip-uboot/arch/nds32/cpu/n1213/ag101/ |
| H A D | timer.c | 21 struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; in timer_init() local
27 writel(0, &tmr->cr); in timer_init()
35 writel(TIMER_LOAD_VAL, &tmr->timer3_load); in timer_init()
36 writel(TIMER_LOAD_VAL, &tmr->timer3_counter); in timer_init()
37 writel(0, &tmr->timer3_match1); in timer_init()
38 writel(0, &tmr->timer3_match2); in timer_init()
44 &tmr->interrupt_mask); in timer_init()
46 cr = readl(&tmr->cr); in timer_init()
51 writel(cr, &tmr->cr); in timer_init()
68 struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; in reset_timer_masked() local
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| /rk3399_rockchip-uboot/arch/microblaze/cpu/ |
| H A D | timer.c | 17 microblaze_timer_t *tmr; variable
21 if (tmr) in get_timer()
30 if (tmr) { in __udelay()
41 tmr->control = tmr->control | TIMER_INTERRUPT; in timer_isr()
63 tmr = (microblaze_timer_t *)base; in timer_init()
79 if (tmr && preload && irq >= 0) { in timer_init()
80 tmr->loadreg = preload; in timer_init()
81 tmr->control = TIMER_INTERRUPT | TIMER_RESET; in timer_init()
82 tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\ in timer_init()
85 ret = install_interrupt_handler (irq, timer_isr, (void *)tmr); in timer_init()
[all …]
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| /rk3399_rockchip-uboot/arch/m68k/lib/ |
| H A D | time.c | 47 timerp->tmr = DTIM_DTMR_RST_RST; in __udelay()
50 timerp->tmr = in __udelay()
88 timerp->tmr = DTIM_DTMR_RST_RST; in timer_init()
99 timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | in timer_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-orion5x/ |
| H A D | timer.c | 26 struct orion5x_tmr_val tmr[2]; member
38 #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
39 #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
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| /rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_hws_hw_training_def.h | 383 #define CNTMR_RELOAD_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x10 + (tmr * 8)) argument
384 #define CNTMR_VAL_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x14 + (tmr * 8)) argument
385 #define CNTMR_CTRL_REG(tmr) (REG_TIMERS_CTRL_ADDR) argument
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| /rk3399_rockchip-uboot/arch/m68k/include/asm/ |
| H A D | timer.h | 22 u16 tmr; /* 0x00 Mode register */ member
34 u16 tmr; /* 0x00 Mode register */
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| /rk3399_rockchip-uboot/drivers/usb/cdns3/ |
| H A D | drd.h | 29 __le32 tmr; member
50 __le32 tmr; member
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sunxi_dw.c | 141 writel(399, &mctl_com->tmr); in mctl_set_master_priority_a64()
168 writel(399, &mctl_com->tmr); in mctl_set_master_priority_h5()
196 writel(399, &mctl_com->tmr); in mctl_set_master_priority_r40()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sunxi_dw.h | 22 u32 tmr; /* 0x0c (unused on H3) */ member
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | nvidia,tegra20-car.txt | 33 5 tmr
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| /rk3399_rockchip-uboot/ |
| H A D | README | 4765 …tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0…
4772 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
4775 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
4778 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
4781 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
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